DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 103

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

18.1.2 STATUS REGISTER FOR THE HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a 1. Some of the bits in these four HDLC status registers are latched and some are real time
bits that are not latched. Section 18.1.4 contains register descriptions that list which bits are latched and
which are not. With the latched bits, when an event occurs and a bit is set to a 1, it will remain set until
the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event
has occurred again. The real time bits report the current instantaneous conditions that are occurring and
the history of these bits is not latched.
Like the other status registers in the DS2196, the user will always proceed a read of any of the four
registers with a write. The byte written to the register will inform the DS2196 which of the latched bits
the user wishes to read and have cleared (the real time bits are not affected by writing to the status
register). The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes
to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1
is written to a bit location, the read register will be updated with current value and it will be cleared.
When a 0 is written to a bit position, the read register will not be updated and the previous value will be
held. A write to the status and information registers will be immediately followed by a read of the same
register. The read result should be logically AND’ed with the mask byte that was just written and this
value should be written back into the same register to insure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously in respect to
their access via the parallel port. This write–read–write (for polled driven access) or write–read (for
interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2196 with higher–order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT pin low
when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
18.1.3 Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC and BOC controller the legacy
FDL circuitry (which is described in Section 18.2) should be disabled and the following bits should be
programmed as shown:
As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following
sequences can be applied:
TCR1.2 = 1 (source FDL data from the HDLC and BOC controller)
TBOC.6 = 1 (enable HDLC and BOC controller)
CCR2.5 = 0 (disable SLC–96 and D4 Fs–bit insertion)
CCR2.4 = 0 (disable legacy FDL zero stuffer)
CCR2.1 = 0 (disable SLC–96 reception)
CCR2.0 = 0 (disable legacy FDL zero stuffer)
IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt)
IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt)
IMR2.2 = 0 (disable legacy FDL match interrupt)
IMR2.1 = 0 (disable legacy FDL abort interrupt).
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