DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 108

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

RHIRA: RECEIVE HDLC INFORMATION REGISTER FRAMER A
(Address = 03 Hex)
RHIRB: RECEIVE HDLC INFORMATION REGISTER FRAMER B
(Address = A3 Hex)
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
(MSB)
RABT
SYMBOL
REMPTY
RCRCE
CBYTE
OBYTE
ROVR
RABT
RVM
POK
RCRCE
POSITION
RHIR.7
RHIR.6
RHIR.5
RHIR.4
RHIR.3
RHIR.2
RHIR.1
RHIR.0
ROVR
NAME AND DESCRIPTION
Abort Sequence Detected. Set whenever the HDLC
controller sees 7 or more 1’s in a row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to
write a byte into an already full receive FIFO.
Valid Message. Set when the HDLC controller has detected
and checked a complete HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO
is empty.
Packet OK. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a valid message (and
hence no abort was seen, no overrun occurred, and the CRC
was correct).
Closing Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a message (whether
the message was valid or not).
Opening Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the first byte of a message.
RVM
108 of 157
REMPTY
POK
CBYTE
OBYTE
(LSB)
DS2196