DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 127

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the
falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
Figure 20-2: TAP CONTROLLER STATE MACHINE
20.3 INSTRUCTION REGISTER AND INSTRUCTIONS
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-
IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS2196 with their respective operational binary codes are shown in Table 20-1.
1
0
Test Logic
Reset
Run Test/
Idle
0
1
0
1
Capture DR
Update DR
1
Select
DR-Scan
Pause DR
Exit2 DR
Shift DR
Exit DR
0
1
0
0
1
0
1
1
0
0
1
0
1
Capture IR
1
Update IR
Pause IR
Select
IR-Scan
Shift IR
Exit2 IR
Exit IR
127 of 157
0
1
1
1
0
0
0
1
1
0
0