DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 13

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

3. PIN FUNCTION DESCRIPTION
Transmit Side Pins
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz primary clock is applied here. Used to clock data through the transmit side formatters. TCLKA/B
can be internally connected to RCLKB/A via the CCR4B.2 control bit.
Signal Name:
Signal Description:
Signal Type:
Transmit NRZ serial data. Sampled on the falling edge of TCLKA or TCLKB. TSERA/B can be internally
connected to RSERB/A via the CCR4B.2 control bit.
Signal Name:
Signal Description:
Signal Type:
When programmed as an input, a pulse at this pin will establish either frame or multiframe boundaries for the
transmit side. Via TCR2A.2 and TCR2B.2, the DS2196 can be programmed to output either a frame or multiframe
pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2A.4 and
TCR2B.4 to output double–wide pulses at signaling frames. See Section 21 for details. TSYNCA/B can be
internally connected to RMSYNCB/A via the CCR4B.2 control bit.
Signal Name:
Signal Description:
Signal Type:
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHCLK is selected, a
192-kHz clock, which pulses high during the LSB of each channel, will be output. If TLCLK is selected, either a 4
kHz or 2 kHz (ZBTSI) demand clock for the TLINK data is output. This output signal is always synchronous with
TCLKA or TCLKB. See Section 21 for details.
Signal Name:
Signal Description:
Signal Type:
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If TCHBLK is selected, a
user programmable output that can be forced high or low during any of the 24 T1 channels is output. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as
Fractional T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–
and–insert applications, for external per–channel loopback, and for per–channel conditioning. See Section 21 for
details. If TLINK is selected, this pin will be sampled on the falling edge of TCLKA or TCLKB for data insertion
into either the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 21 for
details. This signal is always synchronous with TCLKA or TCLKB.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKOA and rising or falling edge of TCLKOB with either bipolar data or NRZ
data out of the transmit side formatter. This pin can be programmed to source NRZ data via the Output Data
Format (CCR1A.6 and CCR1B.6) control bits.
TCLKA/B
Transmit Clock
Input
TSERA/B
Transmit Serial Data
Input
TSYNCA/B
Transmit Sync
Input / Output
TCHCLKA/B / TLCLKA/B
Transmit Channel Clock / Transmit Link Clock
Output
TCHBLKA/B / TLINKA/B
Transmit Channel Block / Transmit Link Data
Input / Output
TPOSOA/B / TNRZA/B
Transmit Positive & NRZ Data Output
Output
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