DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 42

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

CCR3A: COMMON CONTROL REGISTER 3 FRAMER A (Address = 30 Hex)
(MSB)
LIDST
TCLKSRC
SYMBOL
TLOOP
RLOSF
FBCT2
FBCT1
LIDST
RSMS
ECUS
TCLKSRC
POSITION
CCR3A.7
CCR3A.6
CCR3A.5
CCR3A.4
CCR3A.3
CCR3A.2
CCR3A.1
CCR3A.0
RLOS
NAME AND DESCRIPTION
Line Interface TX Digital Signal Tri-state. Tri-state control
for the LIU pins LFSYNC, LCLK and LNRZ.
0 = pins not tri-stated
1 = pins tri-stated
Transmit Clock Source Select. This function allows the user
to internally select MCLK as the clock source for the transmit
side formatter.
0 = TCLK supplied by LOTC mux (see TCR1A.7)
1 = use MCLK for TCLK
Function of the RLOSA/LOTCA Output.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RMSYNCA Multiframe Skip Control. Useful in framing
format conversions from D4 to ESF.
0 = RMSYNCA will output a pulse at every multiframe
1 = RMSYNCA will output a pulse at every other multiframe
F Bit Corruption Type 2. Setting this bit high enables the
corruption of one Ft (D4 framing mode) or FPS (ESF framing
mode) bit in every 128 Ft or FPS bits as long as the bit remains
set.
Error Counter Update Select. Selects the update rate of the
error counters and the period of the One Second Timer
(SR2A.5). See Sections 7 & 8 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
Transmit Loop Code Enable. See Section 12 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD register
F Bit Corruption Type 1. A low to high transition of this bit
causes the next three consecutive Ft (D4 framing mode) or FPS
(ESF framing mode) bits to be corrupted causing the remote
end to experience a loss of synchronization.
RSMS
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FBCT2
ECUS
TLOOP
FBCT1
(LSB)
DS2196