DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 44

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

CCR4A: COMMON CONTROL REGISTER 4 FRAMER A (Address = 11 Hex)
LCLKPOL
PWCLKPOL
BERTMEN
(MSB)
LCLKPOL
SYMBOL
LNRZAIS
RTDLPM
LFAMC
TIRFS
–
PWCLKPOL
POSITION
CCR4A.7
CCR4A.6
CCR4A.5
CCR4A.4
CCR4A.3
CCR4A.2
CCR4A.1
CCR4A.0
BERTMEN
NAME AND DESCRIPTION
LCLK Polarity Select.
0 = data updated on rising edge.
1 = data updated on falling edge.
PCLK/WCLK Polarity Select.
0 = data sampled on falling edge.
1 = data sampled on rising edge.
Transmit BERT Mux Enable.
0 = BERT mux disabled.
1 = BERT mux enabled.
LNRZ AIS Enable.
0 = LNRZ and LFSYNC operate normally.
1 = LNRZ =1, LFSYNC = 0.
Not Assigned. Must be set to 0 when written.
LIU to Framer A Mux Control.
0 = LIU connected on-chip to Framer/Formatter A.
1 = LIU disconnected from Framer/Formatter A.
RX/TX Data Link Pin Mode. Determines the function of the
RCHCLKA/RLCLKA, RCHBLKA/RLINKA,
TCHCLKA/TLCLKA and TCHBLKA/TLINKA pins.
0 = RCHCLKA, RCHBLKA, TCHCLKA, TCHBLKA.
1 = RLCLKA, RLINKA, TLCLKA, TLINKA.
Transmit Idle Registers (TIR) Function Select. See Section
11 for timing details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSERA
(i.e., Per Channel Loopback function)
LNRZAIS
44 of 157
–
LFAMC
RTDLPM
TIRFS
(LSB)