DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 69

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DS2196

Manufacturer Part Number
DS2196
Description
T1 Dual Framer LIU
Manufacturer
Dallas Semiconducotr
Datasheet

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Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and
D). In the D4 framing mode, there are only two framing bits per channel (A and B). In the D4 framing
mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from the
previous multiframe. Hence, whether the framer is operated in either framing mode, the user needs only
to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on
multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status
Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are
frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent
signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also
available at the RSER pin.
TS1A TO TS12A: TRANSMIT SIGNALING REGISTERS FRAMER A
(Address = 70 to 7B Hex)
TS1B TO TS12B: TRANSMIT SIGNALING REGISTERS FRAMER B
(Address = F0 to FB Hex)
A(8)
A(16)
A(24)
B(8)
B(16)
B(24)
A/C(8)
A/C(16)
A/C(24)
B/D(8)
B/D(16)
B/D(24)
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF
framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe
boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing
signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe
Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing
mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4
framing mode, there are only two framing bits per channel (A and B). However in the D4 framing mode,
the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The framer
will load the values in the TSRs into the outgoing shift register every other D4 multiframe.
(MSB)
SYMBOL
D(24)
A(1)
A(7)
A(15)
A(23)
B(7)
B(15)
B(23)
A/C(7)
A/C(15)
A/C(23)
B/D(7)
B/D(15)
B/D(23)
POSITION
B(6)
B(14)
B(22)
A/C(6)
A/C(14)
A/C(22)
A(6)
A(14)
A(22)
B/D(6)
B/D(14)
B/D(22)
TS12.7
TS1.0
A(5)
A(13)
A(21)
B(5)
B(13)
B(21)
A/C(5)
A/C(13)
A/C(21)
B/D(5)
B/D(13)
B/D(21)
NAME AND DESCRIPTION
Signaling Bit D in Channel 24
Signaling Bit A in Channel 1
A(4)
A(12)
A(20)
B(4)
B(12)
B(20)
A/C(4)
A/C(12)
A/C(20)
B/D(4)
B/D(12)
B/D(20)
69 of 157
A(3)
A(11)
A(19)
B(3)
B(11)
B(19)
A/C(3)
A/C(11)
A/C(19)
B/D(3)
B/D(11)
B/D(19)
A(2)
A(10)
A(18)
B(2)
B(10)
B(18)
A/C(2)
A/C(10)
A/C(18)
B/D(2)
B/D(10)
B/D(18)
A(1)
A(9)
A(17)
B(1)
B(9)
B(17)
A/C(1)
A/C(9)
A/C(17)
B/D(1)
B/D(9)
B/D(17)
(LSB)
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
DS2196

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