DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 73

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

TIR1A/TIR2A/TIR3A: TRANSMIT IDLE REGISTERS FRAMER A
(Address = 3C to 3E Hex)
TIR1B/TIR2B/TIR3B: TRANSMIT IDLE REGISTERS FRAMER B
(Address = DC to DE Hex)
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel Loopback;
see Figure 1–1).
TIDRA: TRANSMIT IDLE DEFINITION REGISTER FRAMER A
(Address = 3F Hex)
TIDRB: TRANSMIT IDLE DEFINITION REGISTER FRAMER B
(Address = DF Hex)
11.2 RECEIVE SIDE CODE GENERATION
The Receive Mark Registers (RMR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine
which code is used. The digital milliwatt code is an eight-byte repeating pattern that represents a 1 kHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel. If a bit is
set to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to
0, no replacement occurs.
[Also used for Per–Channel Loopback]
(MSB)
CH16
CH24
(MSB)
TIDR7
CH8
SYMBOLS
SYMBOL
CH1-24
TIDR7
TIDR0
CH15
CH23
CH7
TIDR6
POSITIONS
POSITION
TIR1.0-3.7
TIDR.7
TIDR.0
CH14
CH22
CH6
TIDR5
CH13
CH21
CH5
NAME AND DESCRIPTION
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
NAME AND DESCRIPTION
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
TIDR4
CH12
CH20
CH4
73 of 157
TIDR3
CH11
CH19
CH3
TIDR2
CH10
CH18
CH2
TIDR1
(LSB)
CH17
CH1
CH9
TIR1
TIR2
TIR3
TIDR0
(LSB)
DS2196