DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 83
DS2196
Manufacturer Part Number
DS2196
Description
T1 Dual Framer LIU
Manufacturer
Dallas Semiconducotr
Datasheet
1.DS2196.pdf
(157 pages)
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RSCD2A: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER A
(Address = 1C Hex)
RSCD2B: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER B
(Address = BC Hex)
13.
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a UART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHBLK pins will be held high during the entire corresponding channel time. See the timing in
Section 21 for an example.
(MSB)
SYMBOL
C7
CLOCK BLOCKING REGISTERS
C7
C6
C5
C4
C3
C2
C1
C0
C6
POSITION
RSCD2.7
RSCD2.6
RSCD2.5
RSCD2.4
RSCD2.3
RSCD2.2
RSCD2.1
RSCD2.0
C5
NAME AND DESCRIPTION
Receive Spare Code Definition Bit 7. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 6. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 5. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 4. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 3. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 2. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 1. A Don’t Care if a 1 to
7 bit length is selected.
Receive Spare Code Definition Bit 0. A Don’t Care if a 1 to
7 bit length is selected.
C4
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C3
C2
C1
(LSB)
C0
DS2196
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