DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 91

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

BC2: BERT Control Register 2 (Address = 42 Hex)
Table 15-3: BERT RATE INSERTION SELECT
(MSB)
EIB2
EIB2
SYMBOL
0
0
0
0
1
1
1
1
EIB2
EIB1
EIB0
SBE
TC
–
–
–
EIB1
0
0
1
1
0
0
1
1
EIB1
POSITION
EIB0
BC2.7
BC2.6
BC2.5
BC2.4
BC2.3
BC2.2
BC2.1
BC2.0
0
1
0
1
0
1
0
1
EIB0
No errors automatically inserted
10E-1
10E-2
10E-3
10E-4
10E-5
10E-6
10E-7
NAME AND DESCRIPTION
Error Insert Bit 2. Will automatically insert bit errors at the
prescribed rate into the generated data pattern. Useful for
verifying error detection operation. Refer to Table 15-3 for
details.
Error Insert Bit 1. Refer to Table 15-3 for details.
Error Insert Bit 0. Refer to Table 15-3 for details.
Single Bit Error Insert. A low to high transition will create a
single bit error. Must be cleared and set again for a subsequent
bit error to be inserted.
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
Transmit Pattern Load. A low to high transition loads the
pattern generator with the pattern that is to be generated. This
bit should be toggled from low to high whenever the host
wishes to load a new pattern. Must be cleared and set again for
a subsequent loads.
Error Rate Inserted
SBE
91 of 157
–
–
–
(LSB)
TC
DS2196