DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 92

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

BIR: BERT INFORMATION REGISTER (Address = 43 Hex)
(Refer to Section 7 for explanation of reading latched register bits)
(MSB)
SYMBOL
–
BBCO
SYNC
BECO
RLOS
BED
RA1
RA0
–
RA1
POSITION
BIR.7
BIR.6
BIR.5
BIR.4
BIR.3
BIR.2
BIR.1
BIR.0
RA0
NAME AND DESCRIPTION
Not Assigned. Maybe any value when read.
Receive All 1’s (RA1). A latched bit which is set when 32
consecutive 1’s are received. Allowed to be cleared once a 0 is
received.
Receive All Zeros (RA0). A latched bit which is set when 32
consecutive zeros are received. Allowed to be cleared once a 1
is received.
Receive Loss Of Synchronization (RLOS). A latched bit
which is set whenever the receive BERT begins searching for a
pattern. Once synchronization is achieved, this bit will remain
set until read.
Bit Error Detected (BED). A latched bit which is set when a
bit error is detected. The receive BERT must be in
synchronization for it detect bit errors. Cleared when read. Can
generate interrupts if enabled via IEBED (BC1.6).
BERT Bit Counter Overflow (BBCO). A latched bit which is
set when the 32-bit BERT Bit Counter (BBC) overflows.
Cleared when read and will not be set again until another
overflow occurs. Can generate interrupts if enabled via IEOF
(BC1.5).
BERT Error Counter Overflow (BECO). A latched bit
which is set when the 24-bit BERT Error Counter (BEC)
overflows. Cleared when read and will not be set again until
another overflow occurs. Can generate interrupts if enabled via
IEOF (BC1.5).
Real Time Synchronization Status (SYNC). Real time status
of the synchronizer (this bit is not latched). Will be set when
the incoming pattern matches for 32 consecutive bit positions.
Will be cleared when 6 or more bits out of 64 are received in
error. Can generate interrupts on change of state if enabled via
IESYNC (BC1.7).
RLOS
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BED
BBCO
BEC0
SYNC
(LSB)
DS2196