DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 97

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

ERCA: ERROR RATE CONTROL REGISTER FRAMER A (Address = 80 Hex)
ERCB: ERROR RATE CONTROL REGISTER FRAMER A (Address = 85 Hex)
WNOE
(MSB)
SYMBOL
WNOE
RNOE
TCBE
ER3
ER2
ER1
ER0
CE
RNOE
POSITION
ERC.7
ERC.6
ERC.5
ERC.4
ERC.3
ERC.2
ERC.1
ERC.0
TCBE
NAME AND DESCRIPTION
Write NOE Registers. If the Host wishes to update to the
NOE registers, this bit must be toggled from a 0 to a 1 after
the Host has already loaded the prescribed error count into the
NOE registers. The toggling of this bit causes the error count
loaded into the NOE registers to be loaded into the error
insertion circuitry on the next clock cycle.
updates require that the WNOE bit be set to 0 and then 1 once
again.
Read RNOEL Registers. If the Host wishes to obtain the
latest count of the number of errors left to be inserted by the
error insertion function, then this bit must be toggled from a 0
to a 1. Subsequent reads require that the RNOE bit be set to 0
and then 1 once again. The Host must wait at least 972 ns
(1.5 clock periods) after toggling this bit to read the NOEL
registers. The Host may read the NOEL registers at any time
but they will contain either the count of errors left to be
inserted (after toggling the RNOE bit) or the count of the
number of errors that the Host has loaded (after writing to the
NOE registers).
TCHBLK Enable.
TCHBLK signal should be used to “block” certain channels
from being corrupted. When TCBE is set high, then the error
insertion logic will not corrupt DS0 channels in which the
TCHBLK signal has be programmed high.
0 = all the error insertion logic to corrupt all DS0 channels
1 = allow the error insertion logic to only corrupt the DS0
channels determined by
the TCHBLK signal
Constant Errors. When this bit is set high (and the ER0 to
ER3 bits are not set to 0000), the error insertion logic will
ignore the Number Of Error registers (NOE1A, NOE2A,
NOE1B, and NOE2B) and generate errors constantly at the
selected insertion rate.
registers determine how many errors are to be inserted.
Error Rate Bit 3. Refer to Table 16-1 for details.
Error Rate Bit 2. Refer to Table 16-1 for details.
Error Rate Bit 1. Refer to Table 16-1 for details.
Error Rate Bit 0. Refer to Table 16-1 for details.
CE
97 of 157
ER3
This bit determines whether the
When CE is set to 0, the NOE
ER2
ER1
Subsequent
(LSB)
ER0
DS2196