DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 10

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

DS21Q41B
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the
(DS), ALE(AS), and
(R/
) pins. If BTS=1, then these pins
RD
WR
W
assume the function listed in parentheses ().
Read Input [
] (Data Strobe [DS]).
RD
Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.
Chip Selects [
]. Must be low to read or write to any of the four framers.
CS
A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [
] (Read/Write [R/
]).
WR
W
Positive Supply [V
]. 5.0 volts ±0.5 volts.
DD
Signal Ground [V
]. 0.0 volts.
SS
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