DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 17

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
OUTPUT PIN TEST MODES Table 3-1
TEST1
(MSB)
TEST1
0
0
1
1
SYMBOL
TEST1
TEST0
TSDW
D4YM
ZBTSI
B7ZS
TSIO
TSM
TEST0
TEST0
0
1
0
1
POSITION
TCR2.7
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
TCR2.1
TCR2.0
Operate normally
Force all output pins 3-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
ZBTSI
NAME AND DESCRIPTION
Test Mode Bit 1 for Output Pins. See Table 3-1.
Test Mode Bit 0 for Output Pins. See Table 3-1.
ZBTSI Enable.
0=ZBTSI disabled
1=ZBTSI enabled
TSYNC Double-Wide. (Note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0=do not pulse double-wide in signaling frames
1=do pulse double-wide in signaling frames
TSYNC Mode Select.
0=frame mode (see the timing in Section 12)
1=multiframe mode (see the timing in Section 12)
TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
D4 Yellow Alarm Select.
0=0s in bit 2 of all channels
1=a 1 in the S-bit position of frame 12
Bit 7 0 Suppression Enable.
0=no stuffing occurs
1=Bit 7 force to a 1 in channels with all 0s
TSDW
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EFFECT ON OUTPUT PINS
TSM
TSIO
D4YM
B7ZS
DS21Q41B
(LSB)