DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 21

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

DS21Q41B
PULSE DENSITY ENFORCER
The DS21Q41B always examines both the transmit and receive data streams for violations of the
following rules which are required by ANSI T1.403-1989: - no more than 15 consecutive 0s - at least N
ones in each and every time window of 8 x (N +1) bits where N=1 through 23. Violations for the transmit
and receive data streams are reported in the RIR2.2 and RIR2.1 bits, respectively.
When the CCR3.3 is set to 1, the DS21Q41B will force the transmitted stream to meet this requirement
no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0
since B8ZS encoded data streams cannot violate the pulse density requirements.
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS21Q41B should be configured for operation by writing
to all of the internal registers (this includes setting the Test Registers to 00Hex) since the contents of the
internal registers cannot be predicted on power-up. Finally, after the TSYSCLK and RSYSCLK inputs
are stable, the ESR bit should be toggled from a 0 to a 1 (this step can be skipped if the elastic stores are
disabled).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS21Q41B,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register 1 (RIR1), and Receive
Information Register 2 (RIR2). When a particular event has occurred (or is occurring), the appropriate bit
in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched
fashion. This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again or if the alarm(s) is still present.
The user will always precede a read of these registers with a write. The byte written to the register will
inform the DS21Q41B which bits the user wishes to read and have cleared. The user will write a byte to
one of these four registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions
he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read
register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the
read register will not be updated and the previous value will be held. A write to the status and information
registers will be immediately followed by a read of the same register. The read result should be logically
AND’ed with the mask byte that was just written and this value should be written back into the same
register to insure that the bit does indeed clear. This second write is necessary because the alarms and
events in the status registers occur asynchronously in respect to their access via the parallel port. The
write-read-write scheme is unique to the four status registers and it allows an external microcontroller or
microprocessor to individually poll certain bits without disturbing the other bits in the register. This
operation is key in controlling the DS21Q41B with higher-order software languages.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the
output pin.
INT
All four framers within the DS21Q41B share the
output. Each of the alarms and events in the SR1
INT
and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1
(IMR1) and Interrupt Mask Register 2 (IMR2) respectively. The user can determine which framer has
active interrupts by polling the Interrupt Status Register (ISR).
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