DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 30

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS21Q41B that record bipolar violations, excessive 0s, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on 1-second boundaries as
determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data is
lost. All three counters will saturate at their respective maximum counts and they will not rollover (note:
only the Line Code Violation Count Register has the potential to overflow).
5.1 Line Code Violation Count Register (LCVCR)
Line Code Violation Count Register 1 High (LCVCR1) is the most significant word and LCVCR2 is the
least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar
Violations (BPVs) or excessive 0s. See Table 5-1 for details of exactly what the LCVCRs count. If the
B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter is
always enabled; it is not disabled during receive loss of synchronization (RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address=23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address=24 Hex)
LINE CODE VIOLATION COUNTING ARRANGEMENTS Table 5-1
5.2 Path Code Violation Count Register (PCVCR)
When the receive side of the DS21Q41B is set to operate in the ESF framing mode (CCR2.3=1), PCVCR
will automatically be set as a 12-bit counter that will record errors in the CRC6 code words. When set to
operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing
bit position. Via the RCR2.1 bit, the DS21Q41B can be programmed to also report errors in the Fs
framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1)
conditions. See Table 5-2 for a detailed description of exactly what errors the PCVCR counts.
(MSB)
LCV15
LCV7
COUNT EXCESSIVE
0S? (RCR1.7)
SYMBOL
CV16
CV0
yes
yes
no
no
LCV14
LCV6
POSITION
LCVCR1.7
LCVCR2.0
LCV13
LCV5
B8ZS ENABLED?
LCV12
LCV4
(CCR2.2)
NAME AND DESCRIPTION
MSB of the 16-bit code violation count
LSB of the 16-bit code violation count
yes
yes
no
no
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LCV11
LCV3
BPVs
BPVs + 16 consecutive 0s
BPVs (B8ZS code words not counted)
BPVs + 8 consecutive 0s
WHAT IS COUNTED IN THE LCVCRs
LCV10
LCV2
LCV9
LCV1
LCV8
LCV0
(LSB)
LCVCR1
LCVCR2
DS21Q41B