DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 34

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DS21Q41BTN

Manufacturer Part Number
DS21Q41BTN
Description
Quad T1 Framer
Manufacturer
Dallas Semiconducotr
Datasheet

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states that no more than five 1s should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS21Q41B
will automatically look for five 1s in a row.
If it finds such a pattern, it will automatically insert a 0 after the five ones. The CCR2.4 bit should always
be set to a 1 when the DS21Q41B is inserting the FDL. More on how to use the DS21Q41B in FDL
applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address=7E Hex)
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
7.0 SIGNALING OPERATION
The robbed bit signaling bits in embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by the DS21Q41B. There is a set of 12 registers for the receive side
(RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed
below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is
set to 0, then the robbed signaling bits will appear at RSER in their proper position as they are received. If
CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.
(MSB)
TFDL7
SYMBOL
TFDL7
TFDL0
TFDL6
POSITION
TFDL.7
TFDL.0
TFDL5
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
TFDL4
34 of 61
TFDL3
TFDL2
TFDL1
TFDL0
DS21Q41B
(LSB)

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