DS21Q41BTN Dallas Semiconducotr, DS21Q41BTN Datasheet - Page 9

• Manufacturer Part Number: DS21Q41BTN
• Description: Quad T1 Framer
• Manufacturer: Dallas Semiconducotr

DS21Q41B
Receive Clock [RCLK]. 1.544 MHz primary clock. Used to clock data through the receive side of the
framer.
Receive Channel Clock [RCHCLK]. 192 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data,
locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section 12 for timing
details.
Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low during
any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional
T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications and for per-channel loopback. See Section 12 for timing details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If set to output frame boundaries, then via
RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the receive side
elastic store is enabled, then this pin can be enabled to be an input at which a frame boundary pulse is
applied. See Section 12 for timing details.
Receive Frame Sync (RFSYNC). An extracted 8 kHz pulse, one RCLK wide, is output at this pin which
identifies frame boundaries. See Section 12 for timing details.
Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output should be ignored. See Section 12 for timing details.
Receive Bipolar Data Inputs [RPOS and RNEG]. Sampled on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Allowing this pin
to float can cause the device to 3-state its outputs.
Receive Loss of Sync/Loss of Transmit Clock [RLOS/LOTC]. A dual function output. If CCR1.6=0,
then this pin will toggle high when the synchronizer is searching for the T1 frame and multiframe. If
CCR1.6=1, then this pin will toggle high if the TCLK pin has not been toggled for 5 s.
Receive Alarm Interrupt [
]. Flags host controller during conditions defined in the Status Registers
INT
of the four framers. User can poll the Interrupt Status Register (ISR) to determine which status register in
which framer is active (if any). Active low, open drain output.
3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set
low for normal operation. Useful in board-level testing.
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