DS21Q43A

Manufacturer Part NumberDS21Q43A
DescriptionQuad E1 Framer
ManufacturerDallas Semiconducotr
DS21Q43A datasheet
 
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FEATURES
§ Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
§ All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
§ Frames to FAS, CAS, CCS, and CRC4
formats
§ 8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed buses
§ Each of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz
§ Easy access to Si and Sa bits
§ Extracts and inserts CAS signaling
§ Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
§ Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
§ Detects and generates AIS, remote alarm, and
remote multiframe alarms
§ Pin-compatible with DS21Q41B Quad T1
Framer
§ 5V supply; low power CMOS
§ Available in 128-pin TQFP
§ Industrial (-40°C to +85°C) grade version
available (DS21Q43ATN)
DESCRIPTION
The DS21Q43A combines four of the popular DS2143 E1 Controllers onto a single monolithic die. The
“A” designation denotes that some new features are available in the Quad version which were not
available in the single E1 device. The added features in the DS21Q43A are listed in Section 1. The
DS21Q43A offers a substantial space savings to applications that require more than one E1 framer on a
card. The Quad version is only slightly bigger than the single E1 device. All four framers in the
DS21Q43A are totally independent; they do not share a common framing synchronizer. Also, the transmit
and receive sides of each framer are totally independent. The dual two-frame elastic stores contained in
each of the four framers can be independently enabled and disabled as required. The DS21Q43A meets
all of the latest specifications, including CCITT/ITU G.704, G.706, G.962, and I.431 as well as ETS 300
011 and ETS 300 233.
Quad E1 Framer
FUNCTIONAL DIAGRAM
RECEIVE
FRAMER
TRANSMIT
FORMATTER
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
ACTUAL SIZE
QUAD
FRAMER
1 of 60
DS21Q43A
ELASTIC
STORE
ELASTIC
STORE
E1
092299

DS21Q43A Summary of contents

  • Page 1

    ... Quad version which were not available in the single E1 device. The added features in the DS21Q43A are listed in Section 1. The DS21Q43A offers a substantial space savings to applications that require more than one E1 framer on a card. The Quad version is only slightly bigger than the single E1 device. All four framers in the DS21Q43A are totally independent ...

  • Page 2

    ... INTRODUCTION The DS21Q43A Quad E1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer #3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each of the four framers within the DS21Q43A maintains the same register structure that appeared in the DS2143 ...

  • Page 3

    ... DS21Q43A BLOCK DIAGRAM Figure 1-1 READER’S NOTE This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit timeslots system which are numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on ...

  • Page 4

    ... PIN-OUT CONFIGURATION Figure 1 DS21Q43A ...

  • Page 5

    ... Transmit Bipolar Data from Framer 0 O Transmit Bipolar Data from Framer 1 O Transmit Bipolar Data from Framer 2 O Transmit Bipolar Data from Framer 3 I/O Transmit Sync for Framer 0 I/O Transmit Sync for Framer 1 I/O Transmit Sync for Framer 2 I/O Transmit Sync for Framer DESCRIPTION DS21Q43A ...

  • Page 6

    ... Receive Link Data from Framer 0 O Receive Link Data from Framer 1 O Receive Link Data from Framer 2 O Receive Link Data from Framer 3 I Receive Bipolar Data for Framer 0 I Receive Bipolar Data for Framer 1 I Receive Bipolar Data for Framer DS21Q43A ...

  • Page 7

    ... Receive System Clock for Elastic Store in Framer 2 Receive System Clock for Elastic Store in Framer 3 Receive Loss of Sync/Loss of Transmit Clock from Framer 0 Receive Loss of Sync/Loss of Transmit Clock from Framer 1 Receive Loss of Sync/Loss of Transmit Clock from Framer 2 Receive Loss of Sync/Loss of Transmit Clock from Framer DS21Q43A ...

  • Page 8

    ... Data Bus Bit 5 or Address/Data Bus Bit 5. Data Bus Bit 6 or Address/Data Bus Bit 6. Data Bus Bit 7 or Address/Data Bus Bit 7; MSB. Positive Supply Voltage. Positive Supply Voltage. Positive Supply Voltage. Positive Supply Voltage. Signal Ground. Signal Ground. Signal Ground. Signal Ground DS21Q43A ...

  • Page 9

    ... Transmit Frame Sync [TFSYNC]. 8 kHz pulse. Only used when the transmit side elastic store is enabled. A pulse at this pin will establish frame boundaries for the DS21Q43A. Should be tied low in applications that do not use the transmit side elastic store. See Section 11 for timing details. ...

  • Page 10

    ... Control [TEST]. Set high to 3-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation. ]. Flags host controller during conditions defined in the Status Registers DS21Q43A ...

  • Page 11

    ... A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation (MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex the bus on a positive-going edge. Write Input [ ] (Read/Write [R/ WR Positive Supply [V ]. 5.0 volts ± 0.5 volts. DD Signal Ground [V ]. 0.0 volts. SS DS21Q43A FRAMER DECODE Table 1-5 FS1 (DS), ALE(AS), and ( ]). W ...

  • Page 12

    ... DS21Q43A REGISTER MAP Table 1-6 ADDRESS R BPV or Code Violation Count BPV or Code Violation Count CRC4 Count 1/FAS Error Count CRC4 Error Count E-Bit Count 1/FAS Error Count E-Bit Count Status Status 2. 08 R/W Receive Information. ...

  • Page 13

    ... Transmit Signaling 3. 43 R/W Transmit Signaling 4. 44 R/W Transmit Signaling 5. 45 R/W Transmit Signaling 6. 46 R/W Transmit Signaling 7. 47 R/W Transmit Signaling 8. 48 R/W Transmit Signaling 9. 49 R/W Transmit Signaling 10. 4A R/W Transmit Signaling 11. 4B R/W Transmit Signaling 12. 4C R/W Transmit Signaling 13. 4D R/W Transmit Signaling 14. 4E R/W Transmit Signaling 15 DS21Q43A ...

  • Page 14

    ... Common Control Registers (CCR1, CCR2 and CCR3). Each of the seven registers is described in this section. The Test Registers at addresses 15, 18, and 19 hex are used by the factory in testing the DS21Q43A. On power-up, the Test Registers should be set to 00 hex in order for the DS21Q43A to operate properly. ...

  • Page 15

    ... FAS received in error 3 consecutive times. 1=resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times. Sync Enable. 0=auto resync enabled. 1=auto resync disabled. Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync DS21Q43A (LSB) SYNCE RESYNC ...

  • Page 16

    ... Sa4 bit. Receive Side Backplane Clock Select. 0=if RSYSCLK is 1.544 MHz 1=if RSYSCLK is 2.048 MHz Receive Side Elastic Store Enable. 0=elastic store is bypassed 1=elastic store is enabled Not Assigned. Should be set to 0 when written DS21Q43A ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2 ...

  • Page 17

    ... Transmit Signaling All 1s. 0=normal operation 1=force timeslot 16 in every frame to all 1s TSYNC Mode Select. 0=frame mode (see the timing in Section 11) 1=CAS and CRC4 multiframe mode (see the timing in Section 11) TSYNC I/O Select. 0=TSYNC is an input 1=TSYNC is an output DS21Q43A (LSB) TSM TSIO ...

  • Page 18

    ... TPOS and TNEG are one full TCLK period wide 1=pulses at TPOS and TNEG are 1/2 TCLK period wide Automatic E-Bit Enable. 0=E-bits not automatically set in the transmit direction 1=E-bits automatically set in the transmit direction. Function of RLOS/LOTC Pin. 0=Receive Loss of Sync (RLOS) 1=Loss of Transmit Clock (LOTC DS21Q43A (LSB) AEBE PF ...

  • Page 19

    ... CCR1.0 FRAMER LOOPBACK When CCR1.7 is set the DS21Q43A will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS21Q43A will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1 ...

  • Page 20

    ... CCR2.0 AUTOMATIC ALARM GENERATION When either CCR2.4 or CCR2.5 is set to 1, the DS21Q43A monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) re- ception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the DS21Q43A will either force an AIS alarm (if CCR2 ...

  • Page 21

    ... STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real time status of the DS21Q43A, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set ...

  • Page 22

    ... The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS21Q43A which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with the bit positions he or she wishes to read and the bit positions he or she does not wish to obtain the latest information ...

  • Page 23

    ... CRC Resync Criteria Met. Set when 915/1000 code words are received in error. FAS Resync Criteria Met. Set when 3 consecutive FAS words are received in error. CAS Resync Criteria Met. Set when 2 consecutive CAS MF alignment words are received in error DS21Q43A (LSB) FASRC CASRC ...

  • Page 24

    ... CRC4 mode (CCR1.0=0). This counter is useful for determining the amount of time the DS21Q43A has been searching for synchronization at the CRC4 level. Annex B of ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken ...

  • Page 25

    ... MFs more than two 0s in two frames (512 bits) bit 3 of non-align frame set to 0 for three consecutive occasions in 255-bit times, at least 32 1s are received DS21Q43A (LSB) RCL RLOS ITU SPEC. G.732 4.2 G.732 5 ...

  • Page 26

    ... LOTC pin high if enabled via TCR2.0. Based on RCLK. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every arbitrary boundary if CRC4 is disabled. Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data DS21Q43A (LSB) RCMF TSLIP ...

  • Page 27

    ... Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All 1s. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled DS21Q43A (LSB) RCL RLOS ...

  • Page 28

    ... IMR2.0 5.0 ERROR COUNT REGISTERS There are a set of four counters in the DS21Q43A that record bipolar or code violations, errors in the CRC4 SMF code words, E-bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either 1-second boundaries (CCR2.7=0) or every 62.5 ms (CCR2 ...

  • Page 29

    ... BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the DS21Q43A should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. ...

  • Page 30

    ... MSB of the 10-bit E-Bit count. LSB of the 10-bit E-Bit count. FAS8 FAS7 FAS6 FAS2 FAS1 FAS0 NAME AND DESCRIPTION MSB of the 12-bit FAS error count. LSB of the 12-bit FAS error count DS21Q43A st bit of frames 13 and 15 (LSB) EB9 EB8 EBCR1 EB1 EB0 EBCR2 (LSB) (note 2) ...

  • Page 31

    ... ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS21Q43A provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in Section 6.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is discussed in Section 6 ...

  • Page 32

    ... Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit DS21Q43A (LSB (LSB) Sa6 Sa7 Sa8 ...

  • Page 33

    ... Frame Alignment Signal Bit. Frame Alignment Signal Bit. A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm (used to transmit the alarm). Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit DS21Q43A (LSB (LSB) Sa6 Sa7 Sa8 ...

  • Page 34

    ... The eight settings of receive remote alarm (RA). The eight Sa4 settings in each CRC4 multiframe. The eight Sa5 settings in each CRC4 multiframe. The eight Sa6 settings in each CRC4 multiframe. The eight Sa7 settings in each CRC4 multiframe. The eight Sa8 settings in each CRC4 multiframe DS21Q43A ...

  • Page 35

    ... TSa7 register into the transmit data stream Additional Bit 8 Insertion Control Bit. 0=do not insert data from the TSa8 register into the transmit data stream 1=insert data from the TSa8 register into the transmit data stream DS21Q43A (LSB) Sa6 Sa7 Sa8 ...

  • Page 36

    ... SIGNALING OPERATION The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS21Q43A. Each of the 30 channels has four signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the channel associated with a particular signaling bit ...

  • Page 37

    ... Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled via TCR1.5. On multiframe boundaries, the DS21Q43A will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2 ...

  • Page 38

    ... TRANSMIT IDLE REGISTERS There is a set of five registers in the DS21Q43A that can be used to custom tailor the data that transmitted onto the E1 line channel by channel basis. Each of the 32 E1 channels can be forced to have a user defined idle code inserted into them. ...

  • Page 39

    ... CH19 CH29 CH28 CH27 NAME AND DESCRIPTION Receive Channel Blocking Registers. 0=force the TCHBLK pin to remain low during this channel time 1=force the TCHBLK pin high during this channel time DS21Q43A (LSB) CH2 CH1 RCBR1 (2B) CH10 CH9 RCBR2 (2C) CH18 CH17 ...

  • Page 40

    ... RCR1.6 must be set to 1. The DS21Q43A will always indicate frame boundaries via the RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS (RCR1.7=0) or CRC4 (RCR1 ...

  • Page 41

    ... RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to output just the Sa4 bit. 4. RLINK will always output all five Sa bits as well as the rest of the receive data stream. 5. This diagram assumes the CAS MF begins with the FAS word DS21Q43A ...

  • Page 42

    ... RCHBLK is programmed to block channel 2. 2. RLCLK is programmed to pulse during the Sa4 bits. 3. RLCLK is programmed to pulse during the SA4 and SA8 bits. 4. RLCLK is programmed to pulse during the Sa5 and Sa7 bits. 5. Shown is a non-align frame boundary. 6. There is a 6-RCLK delay from RPOS/RNEG to RSER DS21Q43A ...

  • Page 43

    ... RSYNC is in the input mode (RCR1.5=1). 4. RCHBLK is programmed to block channel 24. RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 11-4 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). 3. RCHBLK is programmed to block channel DS21Q43A ...

  • Page 44

    ... TRANSMIT SIDE TIMING Figure 11-5 NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame DS21Q43A ...

  • Page 45

    ... TSYNC is in the input mode (TCR1.0=0). 2. TSYNC is in the output mode (TCR1.0=1). 3. TCHBLK is programmed to block channel 2. 4. TLINK is programmed to source the Sa4 bits. 5. TLINK is programmed to source the Sa7 and Sa8 bits. 6. Shown is a non-align frame boundary. 7. There is a 5-TCLK delay from TSER to TPOS/TNEG DS21Q43A ...

  • Page 46

    ... G.802 TIMING Figure 11-7 NOTE: 1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 25, and during bit 1 of timeslot 26 DS21Q43A ...

  • Page 47

    ... DS21Q43A SYNCHRONIZATION FLOWCHART Figure 11 DS21Q43A ...

  • Page 48

    ... DS21Q43A TRANSMIT DATA FLOW Figure 11-9 NOTE: 1. TCLK must be tied to RCLK (or RSYSCLK if the elastic store is enabled) and TSYNC must be tied to RSYNC for data to be properly sourced from RSER DS21Q43A ...

  • Page 49

    ... TCLK = RCLK = TSYSCLK = RSYSCLK = 2.048 MHz ; outputs open circuited. 2. 0.0V < V < Applied to when 3-stated. INT -1.0V to +7.0V 0°C to 70°C for DS21Q43AT -40°C to +85°C for DS21Q43ATN -55°C to +125°C 260°C for 10 seconds ( for DS21Q43AT; - +85 C for DS21Q43ATN) SYMBOL MIN TYP 4.50 DD ...

  • Page 50

    ... INTEL BUS READ AC TIMING (BTS=0/MUX=1) Figure 12-1 INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 12 DS21Q43A ...

  • Page 51

    ... 648 SP t 488 DS21Q43A 10% for DS21Q43AT; 10% for DS21Q43ATN) MAX UNITS NOTES ...

  • Page 52

    ... RSYSCLK=2.048 MHz. 3. RSYNC in input mode. RECEIVE SIDE AC TIMING Figure 12-4 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RLCLK and RFSYNC is implied DS21Q43A ns ns ...

  • Page 53

    ... RECEIVE SYSTEM SIDE AC TIMING Figure 12-5 NOTES: 1. RSYNC is in the output mode (RCR 1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). RECEIVE LINE INTERFACE AC TIMING Figure 12 DS21Q43A ...

  • Page 54

    ... CL t 648 SP t 488 DS21Q43A 10% for DS21Q43AT; 10% for DS21Q43ATN) MAX UNITS NOTES ...

  • Page 55

    ... DHR t 0 DHW t 15 ASL t 10 AHL t 20 ASD PW 30 ASH ASED t 20 DDR t 50 DSW DS21Q43A =5V 10% for DS21Q43AT; DD =5V 10% for DS21Q43ATN) TYP MAX UNITS NOTES ...

  • Page 56

    ... TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between TLCLK/TLINk and TSYNC is implied DS21Q43A ...

  • Page 57

    ... SYMBOL MIN DS21Q43A =5V 10% for DS21Q43AT; =5V 10% for DS21Q43ATN) TYP MAX UNITS NOTES ...

  • Page 58

    ... INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 12-10 INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 12- DS21Q43A ...

  • Page 59

    ... MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 12-12 MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 12- DS21Q43A ...

  • Page 60

    ... DS21Q43A 128-PIN TQFP PKG 128-PIN DIM MIN MAX A - 1. 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 21.80 22.20 D1 20.00 BSC E 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.75 56-G4011-001 DS21Q43A ...