DS2407 Dallas Semiconducotr, DS2407 Datasheet

Page 1

... PIO–B 1024 bits user–programmable OTP EPROM 7 bytes of user–programmable status memory to con- trol the device Multiple DS2407s can be identified on a common 1–Wire bus and be turned on or off independently of other devices on the bus Unique, factory–lasered and tested 64–bit registra- tion number (8– ...

Page 2

... CRC, and an 8–bit family code (12h). The 64–bit ROM portion of the DS2407 not only creates an absolutely unique electronic identification for the device itself but also is a means to locate and obtain or change the state of the switches that are associated with the 64– ...

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... LASERED ROM Each DS2407 contains a unique ROM code that is 64 bits long. The first eight bits are a 1–Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3.) The 1– ...

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... DS2407 DS2407 BLOCK DIAGRAM Figure 1 1–WIRE BUS DATA 1–WIRE FUNCTION PROGRAM VOLTAGE DETECT (4 PAGES OF 32 BYTES) PIO–A PIO–B 012099 4/31 PARASITE POWER INT VDD 64–BIT LASERED CONTROL ROM 8–BIT MEMORY SCRATCHPAD FUNCTION CONTROL 16–BIT CRC GENERATOR DATA MEMORY 1024–BIT EPROM ...

Page 5

... HIERARCHICAL STRUCTURE FOR 1–WIRE PROTOCOL Figure 2 1–WIRE BUS BUS MASTER COMMAND LEVEL: 1–WIRE ROM FUNCTION COMMANDS (SEE FIGURE 12) DS2407 SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 6) 64–BIT LASERED ROM Figure 3 8–Bit CRC Code 48–Bit Serial Number MSB LSB MSB ...

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... FINAL STORAGE EPROM 1K BIT 0040H EPROM 32–BYTE FINAL STORAGE EPROM 0060H 32–BYTE FINAL STORAGE EPROM VALID DEVICE POWER–ON DEFAULT SETTINGS SETTINGS (SRAM) DS2407 STATUS MEMORY MAP Figure 5 ADDRESS BIT 7 BIT 6 BIT 5 0 (EPROM (EPROM ...

Page 7

... Conditional Search command later in this data sheet. If both CSS1 and CSS2 in Status Memory Location 7 are set to zero, the DS2407 will enter a “Hidden Mode” where it will keep its status but only responds to Match ROM and Conditional Search. To respond to Conditional Search the polarity (CSS0) needs The “ ...

Page 8

... They may change their status as the user–programmed power–on status is transferred into Status Memory location 7. Bit 7 of Status Memory Loca- tion 7 indicates if the DS2407 is connected to an exter- nal power supply. Without external supply this read– only bit will the voltage applied to the V ...

Page 9

... Redirection Byte only. After the 16–bit CRC of the last page is read, the bus master will receive logical 1s from the DS2407 until a Reset Pulse is issued. The Extended Read Memory command sequence can be ended at any point by issuing a Reset Pulse ...

Page 10

... CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2407) is made entirely by the bus master, since the DS2407 will not be able to determine if the 16–bit CRC calculated by the bus mas- ter agrees with the 16–bit CRC calculated by the DS2407 ...

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... TO FIGURE 6 SECOND PART A5h N EXTENDED READ MEMORY ? Y BUS MASTER T X TA1 (T7:T0) BUS MASTER T X TA2 (T15:T8) DS2407 SETS MEMORY ADDRESS = (T15:T0) BUS MASTER R X REDIR. BYTE BUS MASTER R CRC16 OF COMMAND, X ADDRESS, REDIR. BYTE (1ST PASS) CRC16 OF REDIR. BYTE (SUBSEQUENT PASSES) N CRC ...

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... TO DATA EPROM BUS MASTER R X BYTE FROM EPROM N EPROM BYTE CORRECT ? Y END OF Y DATA MEMORY ? N DS2407 INCREMENTS ADDRESS COUNTER DS2407 LOADS NEW ADDRESS INTO CRC GENERATOR 012099 12/31 TO FIGURE 6 SECOND PART 55h WRITE STATUS ? Y BUS MASTER T X TA1 (T7:T0) BUS MASTER T X TA2 (T15:T8) ...

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... SEE CHANNEL CONTROL BYTE 1 AND FIGURE 7A. Y BUS MASTER T RESET CRC N * ENABLED ? Y N CRC * DUE ? DS2407 INCR. CRC Y BYTE COUNTER Y BUS MASTER T RESET BUS MASTER R CRC16 OF X COMMAND, CONTROL, DATA (1ST PASS) CRC16 OF DATA (SUBSEQUENT PASSES) Y BUS MASTER T RESET ...

Page 14

... The Read Status command is used to read data from the Status Memory field. The functional flow chart of this command is identical to the Read Memory command. Since the Status Memory is only 8 bytes, the DS2407 will send the 16–bit CRC after the last byte of status information has been transmitted. ...

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... DS2407 for channel access. It does not affect reading from or writing to the memory sections of the DS2407. The CRC control bits (bit 0 and bit 1) can be set to create and protect data packets that have the size of 8 bytes or 32 bytes. If desired, the device can safeguard even single bytes by a 16– ...

Page 16

... DS2407 available, bit 6 of the Channel Info Byte reads 1. For 1–channel versions of the DS2407, the PIO B sensed level, channel flip–flop value, and activity latch value should be ignored. Without an external supply, the sup- CHANNEL CONTROL BYTE 1 Figure 7a BIT 7 BIT 6 BIT 5 BIT 4 ...

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... PIO TWO–CHANNEL READ Figure 9B PIO SAMPLING PIO–A PIO–B SYNCHRONOUS MODE 1–WIRE ASYNCHRONOUS MODE 1–WIRE 200 ns < td0 < 300 DS2407 012099 17/31 ...

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... If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. If the 1–Wire bus remains low for more than 5 ms and the DS2407 is not powered externally it may lose its current status and switch off both PIOs. ...

Page 19

... The presence pulse lets the bus master know that the DS2407 is on the bus and is ready to operate. For more details, see the “1–Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the five ROM function commands ...

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... DS2407 DS2407 EQUIVALENT CIRCUIT Figure 10 1–WIRE INTERFACE R DATA Typ 100 MOSFET GROUND BUS MASTER CIRCUIT Figure 11 A) Open Drain PUP BUS MASTER DS5000 OR 8051 EQUIVALENT 5k Open Drain Port Pin 2N7000 T X PGM 2N7000 The interface is reduced to the 5k pull– ...

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... DS2407 T BIT 0 DS2407 T BIT BIT 0 MASTER T BIT BIT 0 BIT 0 MATCH? MATCH BIT 1 DS2407 T BIT BIT 1 DS2407 T BIT BIT 1 MASTER T BIT BIT 1 BIT 1 MATCH? MATCH DS2407 T BIT 63 DS2407 T BIT DS2407 T BIT 63 DS2407 T ...

Page 22

... CSS1 or CSS2 to 1. The Conditional Search Polarity is specified by CSS0. If CSS0 is 0, the DS2407 will respond to a Conditional Search command if the status of the selected source for the specified channel is a logic 0. If CSS0 is set to 1, the source level needs logic 1. For 1– ...

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... DS2407 CSS0 012099 23/31 ...

Page 24

... PDH DS2407 60 s < t < 240 s PDL * In order not to mask interrupt signalling by other devices on the 1–Wire bus, t 960 s. t should be limited to maximum 5 ms. Otherwise the DS2407 may perform a power–on reset cycle. RSTL READ/WRITE TIMING DIAGRAM Figure 15 Write–one Time Slot V PULLUP V ...

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... Pulse. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2407 is shown in Figure 14. A reset pulse followed by a pres- ence pulse indicates the DS2407 is ready to accept a ROM command. The bus master transmits (TX) a reset t REC ...

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... DS2407. This pro- gramming voltage (Figure 16) should be applied for 480 s, after which the bus master should return the data line to an idle high state controlled by the pull– ...

Page 27

... The comparison of CRC values and decision to con- tinue with an operation are determined entirely by the bus master. There is no circuitry on the DS2407 that pre- vents a command sequence from proceeding if the CRC stored in or calculated by the DS2407 does not match the value generated by the bus master ...

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... DS2407 CRC–16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 17 POLYNOMIAL = X 1ST 2ND 3RD 4TH STAGE STAGE STAGE STAGE 9TH 10TH 11TH 12TH 13TH STAGE STAGE STAGE STAGE STAGE 012099 28/ 5TH 6TH ...

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... PUPA 2 –0.3 +0.4 V See graph on page 31 V 6.0 V PUPB =2.8V to 6.0V; – + PUP MIN TYP MAX UNITS 2 –0.3 +0.8 V 4.0 A DS2407 NOTES NOTES 11, 12 NOTES 012099 29/31 ...

Page 30

... DS2407 CAPACITANCE PARAMETER SYMBOL Capacitance DATA Pin C D Capacitance PIO–A Pin C A Capacitance PIO–B Pin C B Capacitance V Pin ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Time Slot t SLOT Write 1 Low Time t LOW1 Write 0 Low Time t LOW0 Read Data Valid t RDV ...

Page 31

... PUP tions should be limited to maximum 5 ms. Otherwise the DS2407 may perform a power–on reset. RSTL 9. Input resistance is to ground. 10. V must be at least 4. connected during a programming pulse. ...