CY2305 Cypress Semiconductor, CY2305 Datasheet

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CY2305

Manufacturer Part Number
CY2305
Description
CY2305 and CY2309 as PCI and SDRAM Buffers
Manufacturer
Cypress Semiconductor
Datasheet

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ALTERA
0
Introduction to Cypress Zero Delay Buffers
What is a Zero Delay Buffer?
A zero delay buffer is a device that can fan out 1 clock signal
into multiple clock signals with zero delay and very low skew
between the outputs. This device is well suited as a buffer for
PCI or SDRAM due to its zero input to output delay and very
low output to output skew.
A simplified diagram of the CY2308 zero delay buffer is shown
in Figure 1. The CY2308 is built using a PLL that uses a ref-
erence input and a feedback input. The feedback loop is
closed by driving the feedback input (FBK) from one of the
outputs. The phase detector in the PLL adjusts the output
frequency of the VCO so that the two inputs have no phase
difference. Since an output is one of the inputs to the PLL,
zero phase difference is maintained from REF to the output
driving FBK. Now if all outputs are uniformly loaded, zero
phase difference will be maintained from REF to all outputs.
This is a simple zero delay buffer. Introducing additional de-
vices (e.g., dividers) between the output and FBK can give
rise to some innovative applications for the PLL, and for fur-
ther information on these refer to the Cypress Application
Note “CY2308 Zero Delay Buffer”. Since many buffering ap-
plications require only a simple closure of the feedback loop,
Cypress has designed zero delay buffers with Internal Feed-
back Loops: the CY2305 and CY2309.
What are the CY2305 and CY2309?
Cypress has designed zero delay buffers especially suited for
use with PCI or SDRAM buffering. The CY2305 and CY2309
have been designed with the feedback path integrated for
simpler system design. A simplified block diagram of the
CY2309 zero delay buffer is shown Figure 2. This zero delay
Cypress Semiconductor Corporation
REF
S2
S1
Figure 1. Simplified Block Diagram of CY2308
Detector
Phase
CY2305 and CY2309 as PCI and SDRAM Buffers
Select Input
Decoding
Loop
Filter
PLL
VCO
MUX
3901 North First Street
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
buffer uses a input/output pad on CLKOUT so that the feed-
back signal can be sensed directly from the output itself.
Drive Capability
The CY2305 and CY2309 have high drive outputs designed
to meet the JEDEC SDRAM specifications of 30 pF capaci-
tance on each DIMM clock input.
Since the typical CMOS input is 7 pF and the CY2305/09 are
designed to drive up to 30 pF; this means that up to 4 CMOS
inputs can be driven from a single output of a CY2305/09.
However the output loading on the CY2305/09 must be equal
on all outputs to maintain zero delay from the input.
Power Down
The CY2305 and CY2309 have a unique power-down mode:
if the input reference is stopped, the part automatically enters
a shutdown state, shutting down the PLL and three-stating the
outputs. When the part is in shutdown mode it draws less than
50 A, and can come out of shutdown mode with the PLL
locked in less than 1 ms. This power down mode can also be
entered by three-stating the input reference driver and allow-
ing the internal pull-down to pull the input LOW (the input
does not have to go LOW, it only has to stop).
5 Volt to 3.3 Volt Level Shifting
The CY2305 and CY2309 can act as a 5-volt to 3.3-volt level
shifter. The reference input pad is 5-volt signal-compatible.
Since many system components still operate at 5 volts, this
feature provides the capability to generate multiple 3.3-volt
clocks from a single 5-volt reference clock. This 5-volt sig-
nal-compatibility is only available on the reference pad; the
other input pads on the CY2309 are not 5-volt compatible.
REF
S2
S1
Figure 2. Simplified Block Diagram of CY2309
Detector
San Jose
Phase
Select Input
Decoding
March 25, 1997 – Revised July 29, 1997
Loop
Filter
PLL
VCO
CA 95134
MUX
408-943-2600
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4

Related parts for CY2305

CY2305 Summary of contents

Page 1

... LOW (the input does not have to go LOW, it only has to stop). 5 Volt to 3.3 Volt Level Shifting The CY2305 and CY2309 can act as a 5-volt to 3.3-volt level shifter. The reference input pad is 5-volt signal-compatible. Since many system components still operate at 5 volts, this feature provides the capability to generate multiple 3 ...

Page 2

... Lead or Lag Adjustments To adjust the lead or lag of the outputs on the CY2305 or CY2309, one must understand the relationships between REF and CLKOUT, and the relationship between CLKOUT and the other outputs. To understand the relationship, first we need to understand a few properties of the CY2305 and CY2309 Phase Locked Loops ...

Page 3

... CLKA4 CLKB1 CLKB4 Advanced CY2305 and CY2309 as PCI and SDRAM Buffers of the outputs is that they all start the rising edge at the same time, but different loads will cause them to have different rise times and different times crossing the measurement thresh- olds. Since CLKOUT is the only output that is monitored, it will ...

Page 4

... Product Information The CY2305 Zero Delay Buffer The CY2305 is a 3.3-volt, five output zero delay buffer in an 8-pin 150-mil SOIC package. This part is intended for buffer- ing one clock into five clocks for PCI buffering or four clocks for use with 1 SDRAM module. The CY2305 is the simplest and easiest to use part in the Cypress zero delay buffer family ...

Page 5

... SDRAM DIMM Zero Delay Buffer Solution The CY2305 is an excellent clocking solution for a system using 1 SDRAM DIMM. The CY2305 comes in a very small 150-mil 8-pin SOIC package and is priced very aggressively for the high volume PC market. There are two solutions for ...

Page 6

... CLKOUT must drive CK0 on the SDRAM module 1 so that CLKOUT is always fully loaded (pin 42 on the SDRAM module). CPUCLK Decoding Logic CY2305 and CY2309 as PCI and SDRAM Buffers The Adjustable Delay Solution: • C must be equal to SDRAM module loading for zero load delay. ...

Page 7

... SDRAM DIMM Zero Delay Buffer Solution The CY2305 and CY2309 are excellent clocking solutions for a system using 3 SDRAM DIMMs. The CY2305 comes in a small 150-mil 8-pin SOIC package and the CY2309 comes in a small 150-mil 16-pin SOIC. Both buffers are priced very aggressively for the high volume PC market ...

Page 8

... SDRAM module). CPUCLK Decoding Logic CY2305 and CY2309 as PCI and SDRAM Buffers • SDRAM modules must be installed in order (module 1 first and module 3 last). • Module 2 and 3 clocks are three-stated when those SDRAM modules are not present, but CLKOUT will contin run. • ...

Page 9

... CPUCLK Decoding Logic Decoding Logic CY2305 and CY2309 as PCI and SDRAM Buffers The Adjustable Delay Solution: • C and C load1 for zero delay. • To make the SDRAM inputs lead or lag the reference input see the Lead or Lag Adjustments section of “ ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2305 and CY2309 as PCI and SDRAM Buffers • SDRAM modules must be installed in order (module 1 first and module 4 last). • ...

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