CY23S02 Cypress Semiconductor, CY23S02 Datasheet
CY23S02
Available stocks
Related parts for CY23S02
CY23S02 Summary of contents
Page 1
... X REF REF Pin Configuration FBIN 1 8 OUT2 VDD GND 3 6 OUT1 FS0 4 5 FS1 , • San Jose CA 95134 • Revised June 7, 2005 CY23S02 OUT2 REF 2 X REF REF REF 2 X REF 4 X REF REF 8 X REF 408-943-2600 ...
Page 2
... FS0 Overview The CY23S02 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” ...
Page 3
... If OUT2 is desired to be rising-edge aligned to the IN input’s rising edge, then connect the OUT2 (i.e., the lowest frequency output) to the FBIN pin. This set-up provides a consistent input-output phase relationship. CY23S02 22Ω OUTPUT 0.1 µ 22Ω ...
Page 4
... =0°C to 70°C or –40° to 85° Test Condition Unloaded, 133 MHz CY23S02 Rating Unit –0.5 to +7.0 V –65 to +150 ° +70 °C –55 to +125 °C 0 3.3V ±5% Min. Typ. Max. — — ...
Page 5
... Power supply stable [6] OUT1 OUT2 Package Type 8-pin SOIC (150 mil) 8-pin SOIC (150 mil) - Tape and Reel 8-pin SOIC (150 mil) 8-pin SOIC (150 mil) - Tape and Reel CY23S02 = 3.3V±5% DD Min. Typ. Max. 10 — 133 20 — 133 — ...
Page 6
... SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] CY23S02 MAX. ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] ...
Page 7
... Document History Page Document Title: CY23S02 Spread Aware™, Frequency Multiplier and Zero Delay Buffer Document Number: 38-07155 Issue REV. ECN NO. Date ** 110265 12/18/01 OBS 292037 See ECN *B 348376 See ECN *C 378857 See ECN Document #: 38-07155 Rev. *C Orig. of Change Description of Change ...