CY24212 Cypress Semiconductor, CY24212 Datasheet

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CY24212

Manufacturer Part Number
CY24212
Description
MediaClock MPEG Clock Generator with VCXO
Manufacturer
Cypress Semiconductor
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY24212SC-3
Quantity:
14
Part Number:
CY24212SC-5
Manufacturer:
SILICON
Quantity:
327
Table 1. CY24212 (-1, -2) Frequency Select Option
Table 2. CY24212 (-3, -5) Frequency Select Option
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *B
Part Number
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
CY24212-1
CY24212-2
CY24212-3
CY24212-5
Pin Configurations
VCXO
Logic Block Diagram
VDD
VSS
XIN
FSEL
FSEL
0
1
0
1
8-pin SOIC
CY24212-1
1
2
3
4
Outputs
1
2
2
2
8
7
6
5
Features
CLKA 27 MHz
VSS
FSEL
XOUT
13.5 MHz/27 MHz (selectable)
13.5 MHz/27 MHz (selectable)
XOUT
VCXO
FSEL
XIN
Reference
Reference
Input Frequency Range
13.5 MHz
27 MHz
27 MHz
27 MHz
OSC
27 MHz
27 MHz
VCXO
VDD
VSS
XIN
3901 North First Street
PRELIMINARY
Q
8-pin SOIC
CY24212-2
1
2
3
4
CLKA/CLKB
MPEG Clock Generator with VCXO
27 MHz
27 MHz
27 MHz
27 MHz
CLKA
8
7
6
5
P
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
27 MHz
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
PLL
CLKB 27 MHz
VCO
CLKA 27 MHz
XOUT
FSEL
VDD
VSS
San Jose, CA 95134
VCXO
VDD
VSS
27.027 MHz
XIN
Output Frequencies
27 MHz
CLKB
DIVIDERS
OUTPUT
CY24212-3,-5
8-pin SOIC
1
2
3
4
Benefits
8
7
6
5
MediaClock™
Revised February 18, 2003
CLKB (27/27.027 MHz)
CLKA 27 MHz
FSEL
XOUT
CLKA (27 MHz)
27 MHz (-2)
27/27.027 MHz (-3)
CY24212
408-943-2600

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CY24212 Summary of contents

Page 1

... XOUT 8 XIN 7 2 VSS VDD 6 3 VCXO FSEL 5 4 CLKA 27 MHz VSS Table 1. CY24212 (-1, -2) Frequency Select Option FSEL Reference 0 13.5 MHz 1 27 MHz Table 2. CY24212 (-3, -5) Frequency Select Option FSEL Reference 0 27 MHz 1 27 MHz Cypress Semiconductor Corporation Document #: 38-07402 Rev. *B ...

Page 2

... Reference Frequency REF Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for ten years. Document #: 38-07402 Rev. *B PRELIMINARY Name Min 0 Min –0.5 [2] –65 V – 0 Min 3.135 0 13.5 CY24212 Typ Max Unit 14 240 ppm + 50 ppm Max Unit 7.0 125 °C 125 ° 0 ...

Page 3

... Output Clock Edge Rate, Measured from 20 pF. See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD Peak-to-peak period jitter 0.1 F DUT GND CY24212 Min Typ Max – – – 50 +150 ...

Page 4

... Voltage and Timing Definitions Clock Output Clock Output Ordering Information Ordering Code Package Name CY24212SC-1 S8 CY24212SC-1T S8 CY24212SC-2 S8 CY24212SC-2T S8 CY24212SC-3 S8 CY24212SC-3T S8 CY24212SC-5 S8 CY24212SC-5T S8 Document #: 38-07402 Rev. *B PRELIMINARY Figure 1. Duty Cycle Definition Figure (0 /t3 (0 Package Type 8-Pin SOIC ...

Page 5

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 8-Lead (150-Mil) SOIC S8 CY24212 51-85066-*A Page ...

Page 6

... Document History Page Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO Document Number: 38-07402 Issue REV. ECN NO. Date ** 117089 09/09/02 *A 120888 12/06/02 *B 123064 02/19/03 Document #: 38-07402 Rev. *B PRELIMINARY Orig. of Change Description of Change CKN New Data Sheet CKN Added -3 CKN Added -5 CY24212 Page ...

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