CY25100 Cypress Semiconductor, CY25100 Datasheet
CY25100
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CY25100 Summary of contents
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... External crystal: 8–30 MHz fundamental crystals — External reference: 8–166 MHz Clock • Integrated phase-locked loop (PLL) • Field-programmable — CY25100SCF and CY25100SIF, 8-pin SOIC — CY25100ZCF and CY25100ZIF, 8-pin TSSOP • Programmable crystal load capacitor tuning array • Low cycle-to-cycle jitter • ...
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... The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread % amounts if required. The input to the CY25100 can be either a crystal or a clock signal. The input frequency range for crystals is 8–30 MHz, and for clock signals is 8–166 MHz. ...
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... Cypress web site at www.cypress.com. Document #: 38-07499 Rev. *D Product Functions Input Frequency (XIN, pin 3 and XOUT The input to the CY25100 can be a crystal or a clock. The input frequency range for crystals MHz, and for clock signals 166 MHz. C ...
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... Capacitance at maximum setting Input pins excluding XIN and XOUT V = 3.45V, Fin = 30 MHz, DD REFCLK = 30 MHz, SSCLK = 66 MHz pF, PD#/OE = SSON LOAD V = 3.45V, Device powered down with DD PD (driven reference pulled down) CY25100 Min. Typ. Max. Unit 8 – 6 – – – values are much 3 – 1 – ...
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... For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer. 3. Since the load capacitors (C and C ) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load XIN XOUT capacitor (C ). Only a single 0.1-µ ...
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... Power-down Timing and Power-up Timing V DD POWER- DOWN 0V CLKOUT (Asynchronous ) Output Enable/Disable Timing V DD OUTPUT ENABLE 0V CLKOUT (Asynchronous ) Document #: 38-07499 Rev )/SR1 (or SR3) DD )/SR2 (or SR4 High Impedance t STP OE2 V IL High Impedance T OE1 CY25100 t PU Page ...
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... atu r e =25C, V DD=3.3V , CLOAD=15p F, SS off 150 200 0 CY25100 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/- 100 120 140 160 180 Time (us) Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/- 100 ...
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... LOA D 2.7 3 3.3 3.6 3.9 VDD (V) Spread=5.0%, C =15pF) LOAD 3 3.3 3.6 3.9 VDD (V) Max Cycle-Cycle Jitter on SSCLK vs. Tem perature (SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/- 2%spread, REFCLK off) 200 175 150 125 100 Tem perature (deg C) CY25100 =15pF) -40C 25C 85C -40C 25C 85C 80 100 Page ...
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... CY25100ZXC-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Commercial 70°C CY25100ZXI-XXXW 8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free CY25100ZXI-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Industrial, –40 to 85°C CY3672 FTG Development Kit ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. DIMENSIONS IN MM[INCHES] MIN. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY25100 MAX. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85093-*A Page ...
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... Document History Page Document Title: CY25100 Field-and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07499 REV. ECN NO. Issue Date ** 126578 06/27/03 *A 128753 08/29/03 *B 130342 12/02/03 *C 204121 See ECN *D 215392 See ECN Document #: 38-07499 Rev. *D Orig. of Change CKN New Data Sheet IJATMP ...