FDC37B77X SMSC Corporation, FDC37B77X Datasheet
FDC37B77X
Related parts for FDC37B77X
FDC37B77X Summary of contents
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... High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry - 480 Address and 15 IRQ Options !" Infrared Port - Multiprotocol Infrared Interface - 32-Byte Data FIFO - IrDA 1.0 Compliant - Consumer IR - SHARP ASK IR FDC37B77x ADVANCED INFORMATION ...
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... DMA channels. The FDC37B77x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced with the board area. The FDC37B77x is software and register compatible with SMSC's proprietary 82077AA core. FDC37B77x 2 ...
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FEATURES ......................................................................................................................... 1 GENERAL DESCRIPTION .................................................................................................. 2 PIN CONFIGURATION........................................................................................................ 5 DESCRIPTION OF PIN FUNCTIONS .................................................................................. 6 DESCRIPTION OF MULTIFUNCTION PINS ......................................................................10 REFERENCE DOCUMENTS ..............................................................................................10 FUNCTIONAL DESCRIPTION............................................................................................12 SUPER I/O REGISTERS ................................................................................................12 HOST PROCESSOR INTERFACE .................................................................................12 FLOPPY DISK CONTROLLER ..........................................................................................13 FDC INTERNAL ...
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DC ELECTRICAL CHARACTERISTICS........................................................................160 TIMING DIAGRAMS .........................................................................................................165 ECP PARALLEL PORT TIMING ......................................................................................186 80 Arkay Dr. Hauppauge, NY 11788 (631) 435-6000 FAX: (631) 273-3123 4 ...
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... PIN CONFIGURATION DRVDEN0 1 DRVDEN1 2 nMTRO 3 4 nPME nDS0 5 CLOCK132 6 VSS nSTEP 9 nWDATA 10 11 nWGATE nHDSEL 12 FDC37B77x nINDEX 13 nTRK0 14 nWRTPRT 15 100 PIN QFP nRDATA 16 nDSKCHG CLOCKI 19 SA0 20 SA1 21 SA2 22 SA3 23 SA4 24 SA5 25 SA6 26 SA7 27 SA8 28 29 SA9 SA10 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (36) 37:40, System Data Bus 42:45 20:30 11-bit System Address Bus 31 Chip Select/SA11 (Note 1) 36 Address Enable 55 I/O Channel Ready 46 ISA Reset Drive 33 Serial IRQ 32 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME 16 Read Disk Data 11 Write Gate 10 Write Disk Data 12 Head Select 8 Step Direction 9 Step Pulse 17 Disk Change 5 Drive Select 0 3 Motor Write ...
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... SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the FDC37B77x addressing modes. Note 2: The "n" as the first letter of a signal name indicates an "Active Low" signal. ...
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Note 7: The “activate” bit for Serial Port 2 (CIrCC) is reset by VTR POR only. The V default for this pin is Logic “1”. Do not use this pin for infrared transceivers that are transmit active high. Buffer Type ...
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DESCRIPTION OF MULTIFUNCTION PINS PIN ORIGINAL NO./QFP FUNCTION nDACK3 51 52 DRQ3 nRI2 92 nDCD2 94 RXD2 95 TXD2 96 nDSR2 97 nRTS2 98 nCTS2 99 nDTR2 100 Note 1: Controlled by DMA3SEL(LD8:CRC0.1) Note 2: Controlled by 8042COMSEL(LD8:CRC0.3) Note 3: ...
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... CPU SD[O:7] INTERFACE * DRQ[1:3] * nDACK[1:3] TC RESET_DRV IOCHRDY CLOCK GEN V Vcc Vss TR CLK32 CLOCKI 32KHz 14MHz FIGURE 1 - FDC37B77x BLOCK DIAGRAM WDT DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL BUS WDATA WCLOCK SMSC PROPRIETARY DIGITAL DATA 82077 SEPARATOR COMPATIBLE WITH WRITE VERTICAL PRECOM- FLOPPYDISK ...
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... Note 1: Refer to the configuration register descriptions for setting the base address FUNCTIONAL DESCRIPTION HOST PROCESSOR INTERFACE The host processor communicates with the FDC37B77x through a series of read/write registers. The port addresses for these registers are shown in Table 1. accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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... Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. supported in the FDC37B77x. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status ...
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... BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Note: In the FDC37B77x only one drive is available at the FDD interface. BIT 2 WRITE GATE Active high status of the WGATE disk interface output ...
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... Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported in the FDC37B77x nDS3 nDS2 1 1 This bit is not gated with ...
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... A logic "1" in this bit will cause the output pin to This go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the FDC37B77x. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the FDC37B77x. Table 3 - Drive Activation Values DRIVE ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 11 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps* 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns *The 2Mbps data rate is only available ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any 7 6 NON DMA RQM DIO BIT 0 ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check ...
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Table 14 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable WP pin became a "1" while the ...
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Table 15 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a ...
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... With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. The FDC37B77x supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In the case of the single transfer, the ...
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Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is ...
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FIFO has <threshold> bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 17 - Description of Command Symbols SYMBOL NAME GAP GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector N Sector Size Code DESCRIPTION Alters Gap 2 ...
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Table 17 - Description of Command Symbols SYMBOL NAME NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative Cylinder Number SC Number ...
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Table 17 - Description of Command Symbols SYMBOL NAME WGATE Write Gate DESCRIPTION Alters timing allow for pre-erase loads in perpendicular drives. 39 ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 18 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command SRT W RECALIBRATE DATA BUS ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result LOCK RELATIVE SEEK DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 22 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 25 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status Terminate the Seek command 3) Read ID - Verify head ...
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Sense Drive Status Sense Drive Status obtains information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values ...
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Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", ...
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Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the ...
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On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled approximately 24 bytes from the start of the Gap2 field. But, ...
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... If an the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37B77x was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems ...
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... Serial Port is shown below. addresses of the serial ports are defined by the configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37B77x contains two serial ports, each of which contain a register set as described below REGISTER NAME ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37B77x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. contents of the Interrupt Enable Register are described below ...
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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 2 Setting this bit to ...
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Table 30 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Highest Second Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit ...
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Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is ...
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Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). indicates that the nDCD input to the chip has changed ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...
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DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 460800 32769 1 Note : The percentage error for all baud rates, except where indicated otherwise, is 0.2%. 2 Note : The High Speed bit is located in the Device Configuration ...
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Table 33 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write Only) DLAB = 0 ADDR = 1 Interrupt ...
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Table 33 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. The IR ...
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... Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The FDC37B77x also provides a mode for support of the floppy disk controller on the parallel port. DATA PORT BASE ADDRESS + 00H ...
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Table 34 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. DATA PORT 0 for a description of operation. This register is only available in EPP mode. ...
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Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (ie a 04H or 05H should be written to the Control port). If the user leaves PCD as ...
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Read Sequence of Operation 1. The host selects an EPP register and drives nIOR active. 2. The chip drives IOCHRDY inactive (low WAIT is not asserted, the chip must wait until WAIT is asserted. 4. The chip tri-states ...
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SData bus for the PData bus. 7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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Table 36 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition Table 37 - ECP Register Definitions NAME ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...
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This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 ...
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Table 39A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data ...
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Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in ...
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FIFO does not cross the threshold. The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the ...
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DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. enabled directly by asserting nPDACK and addresses need not be valid. ...
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An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the ...
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PARALLEL PORT FLOPPY DISK CONTROLLER The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes ...
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CONNECTOR QFP PIN # CHIP PIN # SPP MODE ...
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... A read or write to the Data register. Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. powerdown again when all the powerdown conditions are satisfied. V SUPPORT TR The FDC37B77x requires trickle supply ( provide TR programmable wake-up events in the PME interface when V ...
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... PWRGOOD signal has gone inactive, provided V is powered. The internal TR PWRGOOD signal is also used to determine the clock source for the CIrCC CIR and to disable the IR Half Duplex Timeout. TABLE 43 - FDC37B77x PLL CONTROLS AND SELECTS PLL CONTROL PME POWER (CR24.1) (CR22. ...
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... In order to primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37B77x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn ...
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Table 44 - PC/AT and PS/2 Available Registers AVAILABLE REGISTERS BASE + PC-AT ADDRESS Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23- B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter ...
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... The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2. SERIAL INTERRUPTS The FDC37B77x will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. ...
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B) Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 IRQ15 FRAME FRAME PCICLK IRQSER None IRQ15 Driver 1) Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous ...
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... IRQSER Cycle’s mode. The IRQSER Data Frame Once a Start Frame has been initiated, the FDC37B77x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
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IRQSER PERIOD The SIRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3 was reserved for use by the ...
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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low ...
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The Watchdog Timer Control, SMI Enable and SMI Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses GP Index and Data register to access these registers. ...
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Table 47B - Index and Data Register Normal (Run) Mode INDEX 0x01 0x02 0x03 Access to Watchdog Timer Control (L8 - CRF4) 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Access to SMI Enable Register 1 (L8-CRB4) 0x0D Access ...
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... The FDC37B77x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt WDT_CFG Configuration Register. The FDC37B77x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution 255 seconds with 1 second resolution. ...
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... TST1 P22 P11 Keyboard and Mouse Interface KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37B77x. The Universal Keyboard Controller uses an designed for 8042 microcontroller CPU core. concentrates on the FDC37B77x enhancements to the 8042. For general information about the 8042, refer to the " ...
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... KEYBOARD ISA INTERFACE The FDC37B77x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, Input Data register, and ISA ADDRESS nIOW 0x60 0 1 0x64 0 1 Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read ...
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... CPU-to-Host Communication The FDC37B77x CPU can write to the Output Data register via register DBB. 8042 INSTRUCTION OUT DBB Set OBF, and, if enabled, the KIRQ output signal goes high Host-to-CPU Communication The host system can send both commands and data to the Input Data register. ...
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... Program execution will resume as above. INTERRUPTS The FDC37B77x provides the two 8042 interrupts. IBF and the Timer/Counter Overflow. MEMORY CONFIGURATIONS The FDC37B77x provides 2K of on-chip ROM and 256 bytes of on-chip RAM. Register Definitions Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide ...
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... POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip. DEFAULT RESET CONDITIONS The FDC37B77x has one source of reset: an this bit is external reset via the RESET_DRV pin. Refer to Table 51 for the effect of each type of reset on the internal registers ...
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... GATEA20 AND KEYBOARD RESET The FDC37B77x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 FAST GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 ...
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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of ...
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Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the ...
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... Device 8, The assertion and deassertion of nPME is asynchronous to the PCI clock. FDC37B77x, only active transitions on the ring indicator inputs nRI1 and nRI2, valid NEC infrared remote control frames, active keyboard- clock edges and active mouse-clock edges can assert the nPME signal. Note: The keyboard- ...
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PME Wake Enable register bit, LD8:CRC8, is asserted can cause nPME to become asserted. The PME Wake Status register, LD8:CRC7, indicates which wake source has asserted the nPME signal. The PME PME_Status, LD8:CR6.0, is asserted by active transitions of PME ...
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... POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37B77x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and ...
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CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key ...
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... Notes: HARD RESET: RESET_DRV pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 52 – FDC37B77x Configuration Registers Summary HARD RESET INDEX TYPE GLOBAL CONFIGURATION REGISTERS ...
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HARD VCC RESET POR INDEX TYPE 0xF0 R/W 0x0E 0x0E 0xF1 R/W 0x00 0x00 0xF2 R/W 0xFF 0xFF 0xF4 R/W 0x00 0x00 0xF5 R/W 0x00 0x00 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE ...
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HARD VCC RESET POR INDEX TYPE 0xF1 R/W 0x02 0x02 0xF2 R/W 0x03 0x03 LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD) 0x30 R/W 0x00 0x00 0x70 R/W 0x00 0x00 0x72 R/W 0x00 0x00 0xF0 R/W ...
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HARD RESET INDEX TYPE 0xF6 : - FB Note 1: This register contains some bits that are read or write only. Note 2: Bit 0 is not cleared by HARD RESET. Note 3: CR22 bit 5 and bit 7 are ...
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REGISTER ADDRESS Index Address 0x03 R/W Default = 0x03 on Vcc POR or Reset_Drv 0x04 - 0x06 Reserved - Writes are ignored, reads return 0. Logical Device # 0x07 R/W Default = 0x00 on Vcc POR or Reset_Drv Card Level ...
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REGISTER ADDRESS PowerControl 0x22 R/W Default = 0x00. on Vcc POR or Reset_Drv hardware signal Power Mgmt 0x23 R/W Default = 0x00. on Vcc POR or Reset_Drv hardware signal Note 1: CR22 Bit 5 and Bit 7 are reset by ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04, on Vcc POR or Reset_Drv hardware signal. Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= Vcc POR or Reset_Drv Configuration ...
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REGISTER ADDRESS TEST 4 0x2B R/W Default = 0x00, on Vcc POR TEST 5 0x2C R/W Default = 0x00, on Vcc POR TEST 1 0x2D R/W Default = 0x00, on Vcc POR TEST 2 0x2E R/W Default = 0x00, on ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, ...
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Table 55 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,0x72) Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 on ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 0x62,0x63 BASE I/O RANGE (NOTE3) ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x06 Reserved 0x07 KYBD n/a 0x09 Reserved Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of ...
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For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. For the Serial Port logical device by ...
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Note A. Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Table 59 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Mode Register 0xF0 R/W Default = 0x0E on Vcc POR or Reset_Drv ...
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... Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37B77x supports two floppy drives Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) ...
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Table 60 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on Vcc POR or Reset_Drv PP Mode Register 2 0xF1 R/W Default = 0x00 on Vcc ...
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Table 61 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: To properly share and IRQ, 1. ...
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Table 62 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on Vcc POR or Reset_Drv IR Half Duplex 0xF2 Timeout Default = 0x03 on Vcc ...
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Table 63 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number ...
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Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX SMI Status 0xB6 R/W Register 1 Default = 0x00 on Vcc POR SMI Status 0xB7 R/W Register 2 Default = 0x00 on Vcc POR ...
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... Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET Bit[0] PME_Status = 0 (default Set when FDC37B77x would normally assert the PCI nPME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. ...
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... POR, SOFT RESET or HARD RESET. Writing a “1” to Bit[4:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. This register is used to enable individual FDC37B77x PME wake sources onto the nPME wake bus. When the PME Wake Enable register bit for a wake source is active (“ ...
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Table 65 - nRTS MUXING MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nRTS2 0 1 Table 66 - nCTS2 MUXING MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nCTS2 0 1 Table 67 - nDTR2 MUXING MUX ...
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Table 71 - DRQ3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) DRQ3 1 0 Table 72 - nDACK3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) nDACK3 1 0 UNCONNECTED SELECTED FUNCTION DRQ3 (default) P12 UNCONNECTED SELECTED FUNCTION nDACK3 (default) P16 ...
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Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_TIME_OUT 0xF1 Default = 0x00 on Vcc POR or Reset_Drv WDT_VAL 0xF2 Default = 0x00 on Vcc POR or Reset_Drv WDT_CFG 0xF3 Default = ...
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Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_CTRL 0xF4 Default = 0x00 Cleared by VTR POR DEFINITION Watch-dog timer Control Bit[0] Watch-dog Status Bit, R timeout occurred =0 WD ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V ...
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PARAMETER SYMBOL ICLK2 Input Buffer Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer Low Output Level High Output Level ...
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PARAMETER SYMBOL IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O24PD Type Buffer Low Output Level High Output Level Output Leakage O16SR Type Buffer Low Output ...
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PARAMETER SYMBOL OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level Output Leakage OCLK2 Type Buffer Low Output Level High Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR) OD12 Type Buffer Low Output ...
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PARAMETER V Supply Current Active TR Note 1: All output leakage’s are measured with the current pins in high impedance Note 2: Output leakage is measured with the low driving output off, either for a high level output or a ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used. NAME SD[0:7] IOCHRDY IRQ[3:7,10:12] DRQ[1:3] nWGATE nWDATA nHDSEL nDIR nSTEP nDS0 nMTR0 DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK MDAT ...
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SAx SD<7:0> nIOW FIGURE 2 - IOW TIMING FOR PORT 92 NAME DESCRIPTION t1 SAx Valid to nIOW Asserted t2 SDATA Valid to nIOW Asserted t3 nIOW Asserted to SAx Invalid t4 nIOW Deasserted to DATA Invalid ...
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NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to 4.5V t3 All Host Accesses ...
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AEN SA[x], nCS t1 nIOW SD[x] FINTR PINTR IBF NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], nCS invalid t4 SD[x] Valid to nIOW deasserted t5 ...
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AEN SA[x], nCS t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW SEE TIMING PARAMETERS ON NEXT PAGE DATA VALID t9 t8 FIGURE 5 - ISA READ 169 t13 t6 t5 ...
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NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from nIOR deasserted t6 nIOR deasserted t8 ...
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PCOBF AUXOBF1 nWRT IBF nRD FIGURE 6 - INTERNAL 8042 CPU TIMING NAME DESCRIPTION t1 nWRT deasserted to AUXOBF1 asserted (Notes 1,2) t2 nWRT deasserted to PCOBF asserted (Notes 1,3) t3 nRD deasserted to IBF deasserted (Note 1) Note 1: ...
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CLOCKI FIGURE 7A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32KHZ t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not ...
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AEN FDRQ, PDRQ nDACK t14 nIOR or nIOW DATA (DO-D7) TC FIGURE 8A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay ...
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AEN FDRQ, PDRQ t1 nDACK t14 t11 t6 t5 nIOR or nIOW DATA (DO-D7) TC FIGURE 8B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW ...
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MTR0-1 FIGURE 9 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 10 - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from ...
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PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR FIGURE 11 - PARALLEL PORT TIMING NAME DESCRIPTION t1 PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW t2 PINTR Delay from ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR FIGURE 12A - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t12 ...
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FIGURE 12B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 13A - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t11 ...
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FIGURE 13B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR FIGURE 14A - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t6 t19 t12 t11 ...
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FIGURE 14B - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 15A - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t15 t11 t13 t12 t10 t5 t2 184 t22 ...
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FIGURE 15B - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer ...
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the ...
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PDATA<7:0> nSTROBE t6 BUSY FIGURE 17 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PDATA<7:0> nACK nAUTOFD FIGURE 18 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted (Notes 1,2) t4 nACK Deasserted to nAUTOFD Asserted (Note ...
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DATA IRRX n IRRX Pa rameter t1 Pulse W idth at 1 15kba ud t1 Pulse Wid th at 57.6kba ud t1 Pulse Wid th at 38.4kba ud t1 Pulse Wid th at ...
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DAT IRT X n IRT X t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 ...
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IRRX n IRRX t3 t4 MIRRX IRRX P a ramet er t1 Modulated Out put Bit Time t2 Off Bit Time t3 Modulated Outp ut "On" t4 Modulated Out put ...
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IRTX n IRTX t3 t4 MIRTX MIRTX t1 M odulated Out put Bit Time t2 Off Bit Time t3 M odulated Outp ut "On" odulated Outp ut "Off" ...
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TD/TE H 0.10 A1 -C- MIN MIN DIM 2.80 3.15 .110 .124 A 0.1 0.45 .004 .018 A1 A2 2.57 2.87 .101 .113 D 23.4 24.15 .921 .951 ...
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... FDC37B77x ERRATA SHEET PAGE SECTION/FIGURE/ENTRY 10 Notes 5, 6 and 7 10 Buffer Type Descriptions 125 Table 51 130 PME Support 137 Note 3 139 Note 1 143 Notes 2 and 3 152 Table 62/Note CORRECTION See Italicized Text See Italicized Text See Italicized Text See Italicized Text See Italicized Text ...
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... CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37B77x Rev. 03/24/2000 ...