FDC37M60X SMSC Corporation, FDC37M60X Datasheet
FDC37M60X
Related parts for FDC37M60X
FDC37M60X Summary of contents
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... Address IRQ and Three DMA Options Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes FDC37M60x FEATURES Keyboard Controller - 8042 Software Compatible - 8 Bit Microcomputer - 2k Bytes of Program ROM - 256 Bytes of Data RAM ...
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... FDC37M60x may be reprogrammed through the internal configuration registers. There are 480 power I/O address location options, Serialized IRQ interface, and three DMA channels. The FDC37M60x does not require any external The filter components and is therefore easy to use separator and offers lower system costs and reduced board area ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION .................................................................................................................2 PIN CONFIGURATION.......................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS .................................................................................................6 DESCRIPTION OF MULTIFUNCTION PINS.......................................................................................9 FUNCTIONAL DESCRIPTION..........................................................................................................11 SUPER I/O REGISTERS ..................................................................................................................11 HOST PROCESSOR INTERFACE....................................................................................................11 FLOPPY DISK CONTROLLER.........................................................................................................12 FDC INTERNAL REGISTERS...........................................................................................................12 COMMAND SET/DESCRIPTIONS....................................................................................................36 INSTRUCTION SET .........................................................................................................................40 SERIAL PORT (UART).....................................................................................................................66 INFRARED ...
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MAXIMUM GUARANTEED RATINGS*............................................................................................146 DC ELECTRICAL CHARACTERISTICS ..........................................................................................146 TIMING DIAGRAMS ......................................................................................................................150 ECP PARALLEL PORT TIMING ....................................................................................................171 80 Arkay Dr.. Hauppauge, NY 11788 (516) 435-6000 FAX: (516) 273-3123 4 ...
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... DRVDEN0 1 DRVDEN1 2 nMTRO 3 nDS1 4 nDS0 5 nMTR1 6 VSS 7 nDIR 8 nSTEP 9 nWDATA 10 nWGATE 11 nHDSEL 12 FDC37M60x nINDEX 13 nTRK0 14 nWRTPRT 15 100 PIN QFP nRDATA 16 nDSKCHG 17 VCC 18 CLOCKI 19 nCS/SA11 20 SA10 21 SA9 22 SA8 23 SA7 24 SA6 25 SA5 26 SA4 27 SA3 28 SA2 29 SA1 30 PIN CONFIGURATION SLCT 79 nERROR 78 nACK 77 VSS ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (34) 37:40, System Data Bus 42:45 21:31 11 bit System Address Bus 20 Chip Select/SA11 (Note 1) 34 Address Enable 55 I/O Channel Ready 46 ISA Reset Drive 33 Serial IRQ ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME 12 Head Select 8 Step Direction 9 Step Pulse 17 Disk Change 5 Drive Select 0 4 Drive Select 1 3 Motor Motor Write Protected 14 Track ...
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... SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the FDC37M60x addressing modes. Note 2: The "n" as the first letter of a signal name indicates an "Active Low" signal. ...
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DESCRIPTION OF MULTIFUNCTION PINS Pin No./QFP Original Function Controlled by IRMODSEL(LD8:CRC0.0) and IRRX3SEL(LD8:CRC0.4) 51 nDACK3 DRQ3 52 Controlled by DMA3SEL(LD8:CRC0.1) nRI2 92 nDCD2 94 Controlled by 8042COMSEL(LD8:CRC0.3) RXD2 95 TXD2 96 Controlled by IR Option Register( LD5:CRF1.6) nDSR2 97 nRTS2 ...
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... INTERFACE SD[O:7] DRQ[1:3] nDACK[1:3]* TC RESET_DRV IOCHRDY CLOCK GEN nINDEX Vcc Vss nTRK0 nDSKCHG nWRPRT ICLOCK nWGATE (14.318) FIGURE 1 - FDC37M60x BLOCK DIAGRAM MULTI-MODE DATA BUS ADDRESS BUS CONFIGURATION REGISTERS COMPATIBLE CONTROL BUS WDATA COMPATIBLE WCLOCK PORT 2 WITH SMSC PROPRIETARY DIGITAL 82077 DATA COMPATIBLE ...
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... Note 1: Refer to the configuration register descriptions for setting the base address FUNCTIONAL DESCRIPTION HOST PROCESSOR INTERFACE The host processor communicates with the FDC37M60x through a series of read/write registers. The port addresses for these registers are shown in Table 1. accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 Active high status of ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These two ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2-7 are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy ...
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DIGITAL OUTPUT REGISTER Bit 1 Bit Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. Table 9 - Drive Type ID REGISTER 3F3 - DRIVE TYPE ID Bit 5 ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 13 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps* 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns *The 2Mbps data rate is only available ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any 7 6 RQM DIO NON DMA BIT 0 ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, BIT NO. SYMBOL 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check Head Address 1,0 DS1,0 Drive Select the Data Register contains data bytes ...
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Table 16 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 17 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a ...
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... With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. The FDC37M60x supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In the case of the single transfer, the ...
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Execution Phase All data transfers to or from the FDC during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred ...
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FIFO has <threshold> bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 19 - Description of Command Symbols SYMBOL NAME EOT End of Track GAP GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector N Sector Size Code ...
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Table 19 - Description of Command Symbols SYMBOL NAME NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative Cylinder Number SC Number ...
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Table 19 - Description of Command Symbols SYMBOL NAME WGATE Write Gate DESCRIPTION Alters timing allow for pre-erase loads in perpendicular drives. 39 ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 20 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 -------- ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 24 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 27 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper ...
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The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The Table 29 - Drive Control Delays (ms 500K 0 64 128 256 ...
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FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from bytes. Defaults to one ...
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To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. ...
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Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording enhancement allows ...
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... If an the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37M60x was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems ...
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... Serial Port is shown below. addresses of the serial ports are defined by the configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37M60x contains two serial ports, each of which contain a register set as described below REGISTER NAME ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37M60x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. contents of the Interrupt Enable Register are described below ...
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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift ...
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Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Highest Second Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit logic "0", the nDTR output is forced to ...
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Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection ...
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MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of ...
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Table 33 shows the baud rates possible with a 1.8462 MHz crystal. Effect Of The Reset on Register File The Reset Function Table (Table 34) details the effect of the Reset input on each of the registers of the Serial ...
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XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to ...
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DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 115200 1 230400 32770 460800 32769 *Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%. REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control ...
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Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write Only) DLAB = 0 ADDR = 1 Interrupt ...
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Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. transmission can use the standard ...
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... The FDC37M60x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation ...
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Table 37 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic “1” causes the printer to generate a line feed after each line is printed. A logic “0” means no autofeed. BIT 2 nINIT ...
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EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. DATA PORT 0 for a description of operation. This register is only available in EPP mode. ...
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IOCHRDY allowing the host to complete the write cycle. 8. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. Chip may modify nWRITE and ...
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EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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Table 39 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition Table 40 - ECP Register Definitions NAME ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on ...
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FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. ...
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The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. Table 42A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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Table 43 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded ...
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FIFO does not cross the threshold. The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is ...
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DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. Note: The only way to properly terminate DMA transfers is ...
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FIFO this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a single burst. Programmed I/O - Transfers from ...
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AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management ...
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... In conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37M60x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn ...
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Table 44 - PC/AT and PS/2 Available Registers Base + Address Available Registers PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23- B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter ...
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... SERIAL IRQ The FDC37M60x will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. A) Start Frame timing with source sampled a low pulse on IRQ1 START FRAME PCICLK ...
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B) Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 IRQ15 FRAME FRAME PCICLK IRQSER None IRQ15 Driver H=Host Control, R=Recovery, I=Idle, T=Turn-Around, S=Sample 1) Stop pulse is 2 clocks wide for Quiet ...
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... IRQSER Cycle’s mode. IRQSER Data Frame Once a Start Frame has been initiated, the FDC37M60x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
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... Note: The SIRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3 was reserved for use by the System Management Interrupt (nSMI). The FDC37M60x does not support SMI. IRQSER Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), 6 (RTC), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt ...
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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low ...
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... TST1 P22 P11 Keyboard and Mouse Interface KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37M60x. The Universal Keyboard Controller uses an designed for 8042 microcontroller CPU core. concentrates on the FDC37M60x enhancements to the 8042. For general information about the 8042, refer to the " ...
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... KEYBOARD ISA INTERFACE The FDC37M60x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, Table 48 - ISA I/O Address Map ISA ADDRESS nIOW 0x60 0 1 0x64 0 1 Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read ...
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... CPU-to-Host Communication The FDC37M60x CPU can write to the Output Data register via register DBB. 8042 INSTRUCTION OUT DBB Set OBF, and, if enabled, the KIRQ output signal goes high Host-to-CPU Communication The host system can send both commands and data to the Input Data register. ...
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... INTERRUPTS The FDC37M60x interrupts. IBF and the Timer/Counter Overflow. MEMORY CONFIGURATIONS The FDC37M60x provides 2K of on-chip ROM and 256 bytes of on-chip RAM. Register Definitions Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled ...
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... DEFAULT RESET CONDITIONS interrupt is The FDC37M60x has one source of reset: an external reset via the RESET_DRV pin. Refer to Table 51 for the effect of each type of reset on the internal registers. Table 51 - Resets HARDWARE RESET (RESET) Weak High Weak High ...
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... GATEA20 AND KEYBOARD RESET The FDC37M60x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 FAST GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 ...
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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of ...
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Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the ...
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... POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37M60x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and ...
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CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip Configuration State the Config Key is sent ...
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Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 52 - Configuration Registers INDEX ...
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Table 52 - Configuration Registers INDEX TYPE HARD RESET LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0x74 ...
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Table 52 - Configuration Registers INDEX TYPE HARD RESET LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x30 R/W 0x00 0xC0 R/W 0x06 0xC1 R/W 0x03 0xC2 R - 0xC3 R - 0xC4 R - 0xF6 LOGICAL DEVICE 9 ...
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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when ...
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REGISTER ADDRESS PowerControl 0x22 R/W Default = 0x00. on Vcc POR or Reset_Drv hardware signal Power Mgmt 0x23 R/W Default = 0x00. on Vcc POR or Reset_Drv hardware signal Table 53 - Chip Level Registers DESCRIPTION Bit[0] FDC Power Bit[1] ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04, on Vcc POR or Reset_Drv hardware signal. Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= Vcc POR or Reset_Drv Configuration ...
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REGISTER ADDRESS TEST 4 0x2B R/W Default = 0x00, on Vcc POR TEST 5 0x2C R/W Default = 0x00, on Vcc POR TEST 1 0x2D R/W Default = 0x00, on Vcc POR TEST 2 0x2E R/W Default = 0x00, on ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, ...
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Table 55 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,0x72) Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 on ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 0x62,0x63 0x06 Reserved BASE I/O ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x07 KYBD n/a 0x09 Reserved Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical ...
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Table 58 - DMA Channel Select Configuration Register Description NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 on Vcc POR or Reset_Drv Note: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] ...
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Note A. Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Configuration Table 59 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Mode Register 0xF0 R/W Default = 0x0E on Vcc POR or ...
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... Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37M60x supports two floppy drives Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) ...
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Table 60 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on Vcc POR or Reset_Drv DEFINITION Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = ...
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Table 61 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: To properly share and IRQ, 1. ...
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Table 62 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on Vcc POR or Reset_Drv IR Half Duplex 0xF2 Timeout Default = 0x03 on Vcc ...
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Table 63 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF Table 64 - Auxilliary I/O, Logical Device 8 [Logical Device Number ...
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Table 64 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Floppy Data Rate 0xC2 Select Shadow (R) UART1 FIFO 0xC3 Control Shadow UART2 FIFO 0xC4 Control Shadow DEFINITION Bit[0] Data Rate Select 0 Bit[1] ...
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Table 65 - nRTS MUXING Mux Controls PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nRTS2 0 1 Table 66 - nCTS2 MUXING MUX CONTROLS PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nCTS2 0 1 Table 67 - nDTR2 MUXING MUX ...
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Table 70 - nRI2 MUXING MUX CONTROLS PIN 8042COMSEL. NAME (LD8:CRC0.3) nRI2 0 1 Table 71 - DRQ3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) DRQ3 1 0 Table 72 - nDACK3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) nDACK3 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall ...
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PARAMETER SYMBOL O16SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time OD16P Type Buffer Low Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level Output ...
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PARAMETER SYMBOL Backdrive (PD0-PD7) Suppy Current Active Note 1: All output leakages are measured with the current pins in high impedance Note 2: Output leakage is measured with the low driving output off, either for a high level output or ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used. NAME SD[0:7] IOCHRDY DRQ[1:3] nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK MDAT MCLK ...
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SAx SD<7:0> nIOW FIGURE 2 - IOW TIMING FOR PORT 92 NAME DESCRIPTION t1 SAx Valid to nIOW Asserted t2 SDATA Valid to nIOW Asserted t3 nIOW Asserted to SAx Invalid t4 nIOW Deasserted to DATA Invalid ...
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NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to 4.5V t3 All Host Accesses ...
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AEN SA[x], nCS t1 nIOW SD[x] FINTR PINTR IBF NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], nCS invalid t4 SD[x] Valid to nIOW deasserted t5 ...
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AEN SA[x], nCS t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW SEE TIMING PARAMETERS ON NEXT PAGE DATA VALID t9 t8 FIGURE 5 - ISA READ 154 t13 t6 t5 ...
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NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from nIOR deasserted t6 nIOR deasserted t8 ...
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PCOBF AUXOBF1 nWRT IBF nRD FIGURE 6 - INTERNAL 8042 CPU TIMING NAME DESCRIPTION t1 nWRT deasserted to AUXOBF1 asserted (Notes 1,2) t2 nWRT deasserted to PCOBF asserted (Notes 1,3) t3 nRD deasserted to IBF deasserted (Note 1) Note 1: ...
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CLOCKI FIGURE 7A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318 MHZ t2 Clock High Time/Low Time for 14.318 MHz Clock Rise Time/Fall Time (not shown) RESET_DRV NAME DESCRIPTION t4 RESET width (Note 1) Note 1: ...
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AEN FDRQ, PDRQ nDACK t14 nIOR or nIOW DATA (DO-D7) TC FIGURE 8A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay ...
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AEN FDRQ, PDRQ t1 nDACK t14 t11 t6 t5 nIOR or nIOW DATA (DO-D7) TC FIGURE 8B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW ...
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MTR0-1 FIGURE 9 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 10 - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from ...
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PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR FIGURE 11 - PARALLEL PORT TIMING NAME DESCRIPTION t1 PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW t2 PINTR Delay from ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR FIGURE 12A - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t12 ...
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FIGURE 12B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 13A - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t11 ...
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FIGURE 13B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR FIGURE 14A - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t6 t19 t12 t11 ...
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FIGURE 14B - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 15A - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t15 t11 t13 t12 t10 t5 t2 169 t22 ...
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FIGURE 15B - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer ...
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IEEE 1284 Extended Capabilities Port Protocol PDATA nSTROBE BUSY FIGURE 16 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 DATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 DATA ...
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PDATA<7:0> nSTROBE t6 BUSY FIGURE 17 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PDATA<7:0> nACK nAUTOFD FIGURE 18 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted (Notes 1,2) t4 nACK Deasserted to nAUTOFD Asserted (Note ...
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DATA IRRX n IRRX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse ...
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DATA IRTX n IRTX Parameter t1 Pulse W idth at 115kbaud t1 Pulse W idth at 57.6kbaud t1 Pulse W idth at 38.4kbaud t1 Pulse W idth at 19.2kbaud t1 Pulse W ...
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IRRX n IRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output ...
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DATA IRTX n IRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated ...
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...
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... FDC37M60x ERRATA SHEET PAGE SECTION /FIGURE/ENTRY 7 Description of Pin Functions 9 Description of Multifunction PIns 80 Infrared Interface 81 Parallel Port 108 Serial IRQ 111 Table 47/Note 120 8042 P12 and P16 Functions/2nd Paragraph 124 Table 52 142 Table 64 CORRECTION Pin #2/IR Mode Reference Taken out Row #1 Removed ...
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181 ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. FDC37M60x Rev. 6/6/97 ...