FDC37M81x SMSC Corporation, FDC37M81x Datasheet
FDC37M81x
Related parts for FDC37M81x
FDC37M81x Summary of contents
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... Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - 480 Address IRQ and Three DMA Options FDC37M81x FEATURES • Floppy Disk Available on Parallel Port Pins • Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates ...
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... There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels. The FDC37M81x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The FDC37M81x is software and register compatible with SMSC's proprietary 82077AA core ...
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FEATURES.............................................................................................................................................. 1 GENERAL DESCRIPTION ...................................................................................................................... 2 PIN CONFIGURATION............................................................................................................................ 5 DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 6 Buffer Type Descriptions..................................................................................................................... 9 Description of Multifunction Pins ........................................................................................................10 REFERENCE DOCUMENTS..................................................................................................................10 POWER FUNCTIONALITY ....................................................................................................................12 VCC Power ........................................................................................................................................12 VTR Support ......................................................................................................................................12 Internal PWRGOOD...........................................................................................................................12 Trickle Power Functionality ...
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SYSTEM MANAGEMENT INTERRUPT (SMI) .....................................................................................131 PME SUPPORT....................................................................................................................................132 CONFIGURATION................................................................................................................................133 OPERATIONAL DESCRIPTION ..........................................................................................................164 Maximum Guaranteed Ratings.........................................................................................................164 DC Electrical Characteristics............................................................................................................164 TIMING DIAGRAMS .............................................................................................................................169 4 ...
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... PIN CONFIGURATION DRVDEN0 1 DRVDEN1 2 nMTR0 3 nIO_PME 4 nDS0 5 P17 6 VSS 7 nDIR 8 nSTEP 9 nWDATA 10 nWGATE 11 FDC37M81x nHDSEL 12 13 nINDEX 14 nTRK0 100 PIN QFP nWPRT 15 nRDATA 16 nDSKCHG 17 VTR 18 CLOCKI 19 nCS/SA11 20 SA10 21 SA9 22 SA8 23 24 SA7 SA6 25 SA5 26 SA4 27 SA3 28 SA2 29 SA1 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (36) 45:42, System Data Bus 40:37 31:21 11-bit System Address Bus 20 Chip Select/SA11 (Note 2) 34 Address Enable 55 I/O Channel Ready 46 ISA Reset Drive 33 Serial IRQ 32 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME 7,41, Ground 60, Volt Standby Supply Voltage (Note 7) 16 Read Disk Data 11 Write Gate 10 Write Disk Data 12 Head Select 8 Step Direction 9 Step Pulse 17 Disk ...
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... Note 2: For 12 bit addressing, SA0:SA11 only, nCS should be tied to GND. For 16 bit external address qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the FDC37M81x addressing modes. Note 3: KBDRST is active low. Note 4: The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of internal PWRGOOD ...
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Note 5: Requires external pull-up resistor. Note 6: When SYSOPT function is used on nRTS1/SYSOPT pin, an external pulldown register is required to put the base I/O address for configuration at 0x3F0. An external pullup resistor is required to move ...
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Description of Multifunction Pins PIN ORIGINAL NO./QFP FUNCTION nDACK3 51 DRQ3 52 92 nRI2 94 nDCD2 95 RXD2 96 TXD2 nDSR2 97 nRTS2 98 99 nCTS2 100 nDTR2 Note 1: Controlled by DMA3SEL(LD8:CRC0.1) Note 2: Controlled by 8042COMSEL(LD8:CRC0.3) Note 3: ...
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... SD[O:7] INTERFACE * DRQ[1:3] * nDACK[1:3] TC RESET_DRV IOCHRDY CLOCK GEN V Vcc Vss TR nDSKCHG nWRPRT CLOCKI nWGATE 14MHz FIGURE 1 - FDC37M81x BLOCK DIAGRAM WDT DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL BUS WDATA WCLOCK SMSC PROPRIETARY DIGITAL DATA 82077 SEPARATOR COMPATIBLE WITH WRITE VERTICAL PRECOM- FLOPPYDISK ...
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... The FDC37M81x Volt part. supply is 5 Volts (nominal). See the Operational Description sections and the Maximum Current Values subsection. V SUPPORT TR The FDC37M81x requires max trickle supply ( provide sleep current for the TR programmable wake-up events in the PME interface when V is removed. ...
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... Trickle Power Functionality When the FDC37M81x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert and nIO_PME pin active low. The following lists the wakeup events. • UART1 Ring Indicator • UART2 Ring Indicator • Keyboard data • ...
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... Note 1: Refer to the configuration register descriptions for setting the base address FUNCTIONAL DESCRIPTION HOST PROCESSOR INTERFACE The host processor communicates with the FDC37M81x through a series of read/write The base registers. The port addresses for these registers are shown in Table 1. accomplished through programmed I/O or DMA transfers ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drive. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high ...
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... BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Note: In the FDC37M81x only one drive is available at the FDD interface. BIT 2 WRITE GATE Active high status of the WGATE disk interface output ...
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... BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported in the FDC37M81x nDS3 nDS2 1 1 ...
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... The BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the FDC37M81x. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the FDC37M81x. Table 3 - Drive Activation Values DRIVE ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future TAPE SEL1 (TDR. ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration ...
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Table 8 - Precompensation Delays PRECOMP PRECOMPENSATION 432 DELAY (nsec) <2Mbps 2Mbps* 111 0.00 001 41.67 010 83.34 011 125.00 100 166.67 101 208.33 110 250.00 000 Default Default Default: See Table 12 *2Mbps data rate is only available if ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 11 - Default Precompensation Delays DATA RATE *The 2Mbps data rate MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK Tri- CHG state RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 0 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7,6 IC Interrupt Code 00 - Normal termination of command ...
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Table 14 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 15 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Track Head Address Indicates the status of the HDSEL pin. 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: ...
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... FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. The FDC37M81x supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In the case of the single transfer, the DMA Req goes active at the start of the DMA cycle, and the DMA Req is deasserted after the nDACK ...
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FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but ...
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Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 17 - Description of Command Symbols SYMBOL NAME HLT Head Load The time interval that FDC waits after loading the head and before Time initializing a read or write operation. Refer to the Specify command for actual delays. HUT ...
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Table 17 - Description of Command Symbols SYMBOL NAME PCN Present The current position of the head at the completion of Sense Interrupt Cylinder Status command. Number POLL Polling Disable When set, the internal polling routine is disabled. When clear, ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 18 - Instruction Set READ DATA DATA BUS D5 D4 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W RECALIBRATE DATA BUS D5 ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 DS0 ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index ...
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Table 21 - Skip Bit vs Read Data Command DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED SECTOR READ? 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data RESULTS CM BIT OF DESCRIPTION OF ST2 SET? RESULTS ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 22 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Because data is not transferred to the host, TC cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 25 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 5.25" 4096 ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from the commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ...
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Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the ...
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Sense Drive Status Sense Drive Status obtains information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values ...
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Configure The Configure command is issued to select the special features of the FDC. command need not be issued if the default values of the FDC meet the system requirements. Configure Default Values: EIS - No Implied Seeks EFIFO - ...
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It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working ...
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional ...
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... DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37M81x was designed with software compatibility in mind. compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems ...
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... Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial on Port registers increasing addresses addresses. The FDC37M81x contains two serial ports, each of which contain a register set as described below REGISTER NAME 0 0 Receive Buffer (read) ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37M81x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below ...
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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 2 Setting this bit to ...
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FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Highest Second Second Third 0 ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit ...
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This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error this, it assumes that the framing error was due to the ...
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Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). indicates that the nRI input has changed ...
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D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are ...
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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...
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REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read LSR INTRPT (RCVR Data Ready) ...
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Table 33 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 33 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA 1.0, and Amplitude Shift Keyed IR. The IR transmission can ...
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... The FDC37M81x also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power- up ...
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HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, ...
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BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects ...
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AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this ...
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If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is ...
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EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. • High performance half-duplex forward and reverse channel • Interlocked ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition Table 37 - ...
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Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of ...
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Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the ...
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Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from This prevents interrupts from ...
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Table 39A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal ...
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The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An ...
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DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if ...
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Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty ...
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PARALLEL PORT FLOPPY DISK CONTROLLER The Floppy Disk Control signals are available optionally on the parallel port pins. mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be ...
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CONNECTOR QFP PIN # CHIP PIN # SPP MODE ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management Direct ...
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... This makes the behavior of the pins during powerdown very important. The pins of the FDC37M81x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range ...
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Table 43 - PC/AT and PS/2 Available Registers AVAILABLE REGISTERS BASE + ADDRESS PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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Table 44 - State of System Pins in Auto Powerdown SYSTEM PINS STATE IN AUTO POWERDOWN INPUT PINS nIOR Unchanged nIOW Unchanged SA[0:9] Unchanged SD[0:7] Unchanged RESET_DRV Unchanged DACKx Unchanged TC Unchanged OUTPUT PINS IRQx Unchanged (low) SD[0:7] Unchanged DRQx ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter enters ...
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... The FDC37M81x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams for SER_IRQ Cycle A) Start Frame timing with source sampled a low pulse on IRQ1 START FRAME ...
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... SER_IRQ Cycle’s mode. The SER_IRQ Data Frame Once a Start Frame has been initiated, the FDC37M81x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
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SER_IRQ PERIOD The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can also be used for the System Management ...
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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low ...
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The Watchdog Timer Control, SMI Enable and SMI Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses GP Index and Data register to access these registers. ...
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Table 46B - Index and Data Register Normal (Run) Mode INDEX 0x01 0x02 0x03 Access to Watchdog Timer Control (L8 - CRF4) 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Access to SMI Enable Register 1 (L8-CRB4) 0x0D Access ...
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... The FDC37M81x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG Configuration Register. The FDC37M81x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution 255 seconds with 1 second resolution ...
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... TST1 P22 P11 Keyboard and Mouse Interface KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37M81x. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. concentrates on the FDC37M81x enhancements to the 8042. For general information about the 8042, refer to the " ...
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... KEYBOARD ISA INTERFACE The FDC37M81x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, ISA ADDRESS nIOW 0x60 0 1 0x64 0 1 Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read ...
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... If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the FDC37M81x CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0 ...
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... INTERRUPTS The FDC37M81x provides the two 8042 interrupts. IBF and the Timer/Counter Overflow. MEMORY CONFIGURATIONS The FDC37M81x provides 2K of on-chip ROM and 256 bytes of on-chip RAM. Register Definitions Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide ...
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... DEFAULT RESET CONDITIONS The FDC37M81x has one source of reset: an external reset via the RESET_DRV pin. Refer to Table 50 for the effect of each type of reset on the internal registers. ...
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... GATEA20 AND KEYBOARD RESET The FDC37M81x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. Bit Function 7:6 Reserved. Returns 00 when read 5 Reserved. Returns a 1 when read 4 Reserved. Returns a 0 when read 3 Reserved ...
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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of ...
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Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the ...
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Latches On Keyboard And Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. KINT 8042 FIGURE 2 – KEYBOARD LATCH KLATCH Bit VCC D Q CLR RD 60 128 KINT new ...
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... KINT (default), 1=KINT is the latched 8042 KINT. See the Configuration section for description on these registers. Keyboard and Mouse PME Generation The FDC37M81x sets the associated PME Status bits when the following conditions occur: Active Edge on Keyboard Data Signal (KDAT) Active Edge on Mouse Data Signal (MDAT) These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN bit are set ...
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... PME events. The FDC37M81x has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the keyboard clock and data signals and the mouse clock and data signals from the 8042 ...
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... SYSTEM MANAGEMENT INTERRUPT (SMI) The FDC37M81x implements a group nSMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for transparent power management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip ...
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... ACPI function via the assertion of the nIO_PME signal. In the FDC37M81x, only active transitions on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges (high to low) and active mouse-data edges (high to low) can assert the nIO_PME signal. ...
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... FDC37M81x allows the BIOS to assign resources at POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37M81x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports DATA) ...
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CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,3F0H MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, ; LOGICAL DEVICE 8 ;----------------------------' MOV DX,3F0H ...
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... Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 51 – FDC37M81x Configuration Registers Summary HARD RESET INDEX TYPE GLOBAL CONFIGURATION REGISTERS ...
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HARD VCC RESET POR INDEX TYPE LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x00 0x60, R/W 0x00, 0x00, 0x61 0x00 0x00 0x70 R/W 0x00 0x00 ...
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HARD RESET INDEX TYPE 0xB6 R/W - 0xB7 R/W - 0xC0 R/W 0x02 0xC1 R/W 0x01 0xC2 R - 0xC3 R - 0xC4 R - 0xC5 R/W - 0xC6 R/W- - CLEAR 0xC7 R/W- - CLEAR 0xC8 R/W - 0xF1 ...
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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits REGISTER ADDRESS 0x00 - 0x01 Config ...
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REGISTER ADDRESS Card Level Reserved 0x08 - 0x1F Reserved - Writes are ignored, reads return 0 . Device ID 0x20 R Hard wired = 0x4D Device Rev 0x21 R Hard wired = Current Revision PowerControl 0x22 R/W Default = 0x00. ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04, on VCC POR, VTR POR and HARD RESET Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= VCC POR and HARD ...
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REGISTER ADDRESS TEST 4 0x2B R/W Default = 0x00, on VCC POR and VTR POR TEST 5 0x2C R/W Default = 0x00, on VCC POR and VTR POR TEST 1 0x2D R/W Default = 0x00, on VCC POR and VTR ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports six logical units and has six sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, ...
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Table 54 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,0x72) Defaults : 0x70 = 0x00 or 0X06 (Note 3) on VCC POR, VTR POR, SOFT RESET and HARD RESET 0x72 = 0x00, on VCC POR, VTR POR, ...
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Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. Note 3: The default ...
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Table 55 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x06 Reserved 0x07 KYBD n/a 0x08 Auxilary I/O n/a 0x09 Reserved n/a Config. Config. 0x26,0x27 Port (Note 2) Port Note 1: This chip uses ...
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Table 56 - Interrupt Select Configuration Register Description NAME REG INDEX Interrupt 0x70 (R/W) Request Level Select 0 Default = 0x00 or 0X06 (Note 1) on VCC POR, VTR POR, SOFT RESET and HARD RESET Note: An Interrupt is activated ...
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Table 57 - DMA Channel Select Configuration Register Description NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 or 0X02 (Note 1) on VCC POR, VTR POR, SOFT RESET and HARD RESET Note: A DMA channel is activated ...
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Note A. Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by ...
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... Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37M81x supports two floppy drives Reserved, Read as 0 (read only) Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) ...
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Table 59 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on VCC POR, VTR POR and HARD RESET PP Mode Register 2 0xF1 R/W Default = ...
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Table 60 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET Note 1: To properly share ...
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Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on VCC POR, VTR POR and HARD RESET IR Half Duplex 0xF2 Timeout Default = ...
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Table 62 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET 0xF1 - 0xFF Table 63 - Auxiliary I/O, Logical Device 8 ...
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NAME REG INDEX SMI Enable Register 0xB4 R/W 1 Default = 0x00 on VCC POR and VTR POR SMI Enable Register 0xB5 R/W 2 Default = 0x00 on VCC POR and VTR POR Bit 1 is set to ‘1’ on ...
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Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX 2 Default = 0x00 on VCC POR and VTR POR Default = 0x00 0xB8 R/W on VTR POR Pin Multiplex 0xC0 Controls Default = ...
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... Bit[7:1] Reserved PME_En is not affected by VCC POR, SOFT RESET or HARD RESET Bit[0] PME_Status = 0 (default Set when FDC37M81x would normally assert the PCI nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. ...
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Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX Bit[0] Reserved Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[7:5] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT ...
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Table 64 - nRTS MUXING MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nRTS2 0 1 Table 65 - nCTS2 MUXING MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nCTS2 0 1 Table 66 - nDTR2 MUXING MUX ...
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Table 70 - DRQ3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) DRQ3 1 0 Table 71 - nDACK3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) nDACK3 1 0 UNCONNECTED SELECTED FUNCTION DRQ3 (default) P12 UNCONNECTED SELECTED FUNCTION nDACK3 (default) P16 ...
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Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_TIME_OUT 0xF1 Default = 0x00 on VCC POR, VTR POR and HARD RESET WDT_VAL 0xF2 Default = 0x00 on VCC POR, VTR POR and ...
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Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_CTRL 0xF4 Default = 0x00 on VCC POR, VTR POR and HARD RESET DEFINITION Watch-dog timer Control Bit[0] Watch-dog Status Bit, R ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range.....................................................................................................0 Storage Temperature Range ..................................................................................................... -55 Lead Temperature Range........................................................................... Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground ...........................................................................V Negative Voltage on any pin, with respect to Ground............................................................................... ...
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PARAMETER SYMBOL O4 Type Buffer Low Output Level High Output Level Output Leakage IO8 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time O24 ...
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PARAMETER SYMBOL O12 Type Buffer Low Output Level High Output Level Output Leakage O24PD Type Buffer Low Output Level High Output Level Output Leakage O16SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time OD16P ...
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PARAMETER SYMBOL ChiProtect (SLCT, PE, BUSY, nACK, nERROR) OD12 Type Buffer Low Output Level Output Leakage Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) V Supply Current Active CC (Note 4) Trickle Supply Voltage V Supply Current Active TR (Note 4) ...
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1MHz; V CAPACITANCE T A PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance = 5V CC LIMITS MIN TYP MAX OUT 168 TEST UNIT CONDITION ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. NAME SD[7:0] PD[7:0] DRQx nDIR nSTEP nDS0-1 nMTR0-1 nWDATA nRTSx nDTRx nINIT nSTROBE nALF nSLCTIN IOCHRDY TXD1 TXD2 KDAT KCLK MDAT MCLK SER_IRQ CAPACITANCE TOTAL ...
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SAx SD<7:0> nIOW FIGURE 4 - IOW TIMING FOR PORT 92 NAME DESCRIPTION t1 SAx Valid to nIOW Asserted t2 SDATA Valid to nIOW Asserted t3 nIOW Asserted to SAx Invalid t4 nIOW Deasserted to DATA Invalid ...
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FIGURE 5 - POWER-UP TIMING NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to ...
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AEN SA[x], nCS t1 nIOW SD[x] NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], nCS invalid t4 SD[x] Valid to nIOW deasserted t5 SD[x] Hold from ...
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AEN SA[x], nCS nIOR SD[x] PD[x], nERROR, PE, SLCT, nACK, BUSY nIOR/nIOW NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to ...
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CLK CLK KCLK MCLK KDAT/ Start Bit Bit 0 MDAT FIGURE 8 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME DESCRIPTION t1 Time from DATA transition to falling edge of CLOCK (Receive) t2 Time from ...
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CLOCKI FIGURE 9A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHz (Note) t2 Clock High Time/Low Time for 14.318MHz Clock Rise Time/Fall Time (not shown) Tolerance is ± 0.01% Note ...
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AEN FDRQ, PDRQ nDACK[x] t14 nIOR or nIOW SD<7:0> TC FIGURE 10A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay from ...
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AEN FDRQ, PDRQ t1 nDACK[x] t14 t11 t6 t5 nIOR or nIOW SD<7:0> TC FIGURE 10B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 ...
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FIGURE 11 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP ...
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FIGURE 12A - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW Data Start TXD1, 2 FIGURE 12B – SERIAL PORT DATA NAME DESCRIPTION t1 Serial Port Data Bit Time Note 1: tBR is 1/Baud ...
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PD<7:0> nIOW nINIT, nSTROBE, nALF, SLCTIN FIGURE 13 - PARALLEL PORT TIMING NAME DESCRIPTION t1 PD0-7, nINIT, nSTROBE, nALF Delay from nIOW t2 PD0 - PD7 Delay from IOW Active t2 MIN 180 t1 TYP MAX UNITS 100 ns 100 ...
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SA<10:0> SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATASTB nADDRSTB nWAIT FIGURE 14 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t12 t11 t4 t15 ...
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TABLE 73 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 15 - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t11 ...
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TABLE 74 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR FIGURE 16 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t6 t19 t12 t11 ...
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TABLE 75 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 17 - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t15 t11 t13 t12 t10 t5 t2 187 t22 ...
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TABLE 76 - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direc- tion using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. ...
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PD<7:0> nSTROBE BUSY FIGURE 18 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 PDATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 PDATA Hold from nSTROBE Inactive (Note ...
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PD<7:0> nSTROBE t6 BUSY FIGURE 19 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PD<7:0> nACK nALF FIGURE 20 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted (Note ...
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DATA IRRX n IRRX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width ...
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DATA IRTX n IRTX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse ...
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DATA IRRX n IRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated ...
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DATA IRTX n IRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated ...
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TD/TE H 0. DIM 2.80 3.15 .110 .124 A 0.1 0.45 .004 .018 A1 A2 2.57 2.87 .101 .113 D 23.4 24.15 .921 .951 ...
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... CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37M81x Rev. 11/03/06 ...