MD1810 Supertex, Inc., MD1810 Datasheet

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MD1810

Manufacturer Part Number
MD1810
Description
High Speed Quad Mosfet Driver
Manufacturer
Supertex, Inc.
Datasheet

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Features
Applications
Typical Application Circuit
6.0ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2 to 5.0V input CMOS compatible
5.0 to 12V total supply voltage
Smart logic threshold
Low jitter design
Four matched channels
Outputs can swing below ground
Output is high impedence when disabled
Low inductance package
High-performance thermally-enhanced
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
CCD Clock driver/buffer
High speed level translator
3.3V CMOS
Logic Inputs
High Speed Quad MOSFET Driver
OE
INA
INB
INC
IND
+12V
0.47μF
MD1810
GND
VDD
VSS
VH
VL
+12V
OUTA
OUTB
OUTC
OUTD
0.47μF
10nF
10nF
10nF
10nF
General Description
The Supertex MD1810 is a high-speed quad MOSFET
driver. It is designed to drive high voltage P- and N-channel
MOSFETs for medical ultrasound imaging applications. The
MD1810 can also be used for ultrasound metal flaw detection,
nondestructive evaluation test, piezoelectric transducer drive,
clock drive, and PIN diode drive.
The MD1810 has four inputs which individually control four
outputs. It also has an output enable (OE) pin. When OE is low,
all of the outputs will be in a high impedence state regardless
of their logic input control. When OE is high, the MD1810 sets
the threshold logic transition to (V
transition to always be at half the amplitude of the logic input
signal. This allows the device to have inherent propagation
delay matching regardless of the logic input amplitude.
The output stage of the MD1810 has separate power
connections enabling the output signal L and H levels to be
chosen independently from the V
As an example, the input logic levels may be 0 and 1.8 volts,
the control logic may be powered by +5.0 and -5.0 volts, and
the output L and H levels may be varied anywhere over the
range of -5.0 to +5.0 volts. The output stage is capable of
peak currents of up to ±2.0 amps, depending on the supply
voltages used and load capacitance present.
TC6320
TC6320
+10V
-100V
+100V
-10V
1.0μF
1.0μF
1.0μF
1.0μF
OE
DD
+V
and V
GND
)/2. This ensures the
SS
supply voltages.
MD1810

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MD1810 Summary of contents

Page 1

... It also has an output enable (OE) pin. When OE is low, all of the outputs will high impedence state regardless of their logic input control. When OE is high, the MD1810 sets the threshold logic transition to (V transition to always be at half the amplitude of the logic input signal ...

Page 2

... V - 0 0 1 MD1810 16 1 16-Lead QFN (K6) (top view Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = “Green” Packaging 16-Lead QFN (K6) = 3.3V 25° Units Conditions V --- V --- V --- V --- mA No input transitions µA mA One channel on at 5.0Mhz, ...

Page 3

... I = 50mA SOURCE A --- A --- = 3.3V 25° Units Conditions ns Logic input edge speed requirement 1000pF, see timing diagram LOAD ns Input signal rise/fall time 2.0ns For each channel ns ns Device to device delay match Curve OE/2 0. 1.0 2.0 3.0 4.0 5.0 MD1810 V OE ...

Page 4

... INB INC IND MD1810 VSS VL VDD Level Shifter VSS VDD Level Shifter VSS VDD VSS VDD Level Shifter VSS VDD VSS VDD Level Shifter VSS VDD VSS VDD Level Shifter SUB GND VSS 4 MD1810 VH OUTA VL VH OUTB VL VH OUTC VL VH OUTD VL ...

Page 5

... TC6320TG +5.0V 0.47μF 0.47μF 10nF OUTA 10nF Supertex OUTB TC6320 OUTC OUTD GND -5.0V -5.0V 0.47μF 0.47μF Supertex Supertex MD1810 TC2320 5 MD1810 +100V 0.1µF To Piezoelectric Transducer -100V 0.1µF +100V 0.1µF To Piezoelectric Transducer -100V 0.1µF +100V 0.1µF To Piezoelectric Transducer -100V 0.1µF ...

Page 6

... Application Information For proper operation of the MD1810, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND where V ...

Page 7

... Output enable logic input. When OE is high, (V between logic level high and low. When OE is low, all outputs are at high impedance. Keep OE low until IC powered up. The IC substrate is internally connected to the thermal pad. Thermal pad and VSS must be connected externally. 7 MD1810 +V )/2 sets the threshold transition OE GND ...

Page 8

... This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings not to scale. Supertex Doc.#: DSPD-16QFNK64X4P065, Version A061808. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-MD1810 B062408 θ ...

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