IDT72V851L15PF8 IDT, Integrated Device Technology Inc, IDT72V851L15PF8 Datasheet

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IDT72V851L15PF8

Manufacturer Part Number
IDT72V851L15PF8
Description
IC FIFO SYNC 4096X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V851L15PF8

Function
Asynchronous
Memory Size
72K (4K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V851L15PF8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V851L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
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DESCRIPTION:
dual synchronous (clocked) FIFOs. The device is functionally equivalent to
two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are
WRITE CONTROL
WRITE POINTER
WCLKA
RESET LOGIC
LOGIC
WENA1
RSA
WENA2
OEA
OUTPUT REGISTER
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
INPUT REGISTER
256 x 9, 512 x 9,
RAM ARRAY
DA
QA
0
0
- DA
- QA
8
8
3.3 VOLT DUAL CMOS SyncFIFO™
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
OFFSET REGISTER
READ CONTROL
READ POINTER
RCLKA
RENA1
LOGIC
LOGIC
FLAG
RENA2
LDA
EFA
PAEA
PAFA
FFA
1
IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).
Data is written into each of the two arrays on every rising clock edge of the Write
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to Empty+7 for PAEA and
PAEB, and Full-7 for PAFA and PAFB.
lends itself to many flexible configurations such as:
technology.
WRITE CONTROL
WCLKB
WRITE POINTER
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
RESET LOGIC
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
The output port of each FIFO bank is controlled by its associated clock pin
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture
This FIFO is fabricated using IDT's high-performance submicron CMOS
LOGIC
WENB1
RSB
WENB2
OEB
OUTPUT REGISTER
1,024 x 9, 2,048 x 9,
INPUT REGISTER
4,096 x 9, 8,192 x 9
256 x 9, 512 x 9,
RAM ARRAY
DB
QB
0
0
- DB
- QB
8
8
OFFSET REGISTER
OCTOBER 2008
READ CONTROL
READ POINTER
RCLKB
LOGIC
LOGIC
RENB1
FLAG
RENB2
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
LDB
4093 drw 01
DSC-4093/4
EFB
PAEB
PAFB
FFB

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IDT72V851L15PF8 Summary of contents

Page 1

FEATURES: • • • • • The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs • • • • • The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs • • • • • The IDT72V821 ...

Page 2

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN CONFIGURATION ...

Page 3

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN DESCRIPTIONS The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs, referred to as FIFO A ...

Page 4

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage with TERM Respect ...

Page 5

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V ...

Page 6

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL SIGNAL DESCRIPTIONS FIFO A and FIFO B are identical in every ...

Page 7

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL contains four 8-bit offset registers which can be loaded with data ...

Page 8

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS Full Flag ...

Page 9

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) ...

Page 10

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB) QA ...

Page 11

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL WRITE WCLKA (WCLKB) t SKEW1 ...

Page 12

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLKH WCLKA (WCLKB) WENA1 (WENB1 WENA2 (WENB2) (If Applicable) PAFA ...

Page 13

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLK t CLKH WCLKA (WCLKB) t LDA (LDB) t ENS ...

Page 14

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION — When FIFO A (B) is ...

Page 15

IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL TWO PRIORITY DATA BUFFER CONFIGURATION The two FIFOs contained in the ...

Page 16

DEPTH EXPANSION — These FIFOs can be adapted to applications that require greater than 256/512/1,024/2,048/4,096/8,192 words. The exist- ence of double enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are ...

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