IRCC

Manufacturer Part NumberIRCC
DescriptionINFRARED COMMUNICATIONS CONTROLLER
ManufacturerSMSC Corporation
IRCC datasheet
 
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Page 1/79

Download datasheet (435Kb)Embed
Next
Infrared Communications Controller
Multi-Protocol Serial Communications
Controller
Full IrDA v1.1 Implementation: 2.4Kbps,
115.2Kbps, .576Mbps, 1.152Mbps and
4Mbps
Consumer Infrared (TV Remote Control)
Interface
SHARP Amplitude Shift Keyed Infrared
(ASK IR) Interface
Direct Rx/Tx Infrared Diode Control (Raw)
and General Purpose Data Pins
This
document
describes
the
Communications Controller (IrCC) function which
is common to a number of SMSC products
including the FDC37C669FR, FDC37C93xFR,
and FDC37C957FR devices. The IrCC consists
of two main architectural blocks:
16550A
UART
and
a
Communications Engine (SCE) (Figure 2). Each
block is supported by its own unique register set.
FEATURES
Programmable High-Speed Synchronous
Communications Engine (SCE) with a 128-
Byte FIFO and Programmable Threshold
High-Speed NS16C550A-Compatible
Universal Asynchronous Receiver/
Transmitter Interface (ACE UART2) with 16-
Byte Send and Receive FIFOs
ISA Single-Byte and Burst-Mode DMA and
Interrupt-Driven Programmed I/O with Zero
Wait State and String Move Timing
16-bit CRC-CCITT and 32-bit IEEE 802
CRC32 Hardware CRC Generators
GENERAL DESCRIPTION
Infrared
The IrCC UART-driven IrDA SIR and SHARP
ASK modes are backward-compatible with early
SMSC
Super
implementations. The IrCC SCE supports IrDA
v1.1
.576Mbps,
the ACE
Consumer IR modes. All of the SCE modes use
Synchronous
DMA. The IrCC offers flexible signal routing and
programmable output control through the Raw
mode interface, General Purpose Data pins and
Output Multiplexer. Chip-level address decoding
is required to access the IrCC register sets.
I/O
and
Ultra
I/O
infrared
1.152Mbps,
4Mbps,
and

IRCC Summary of contents

  • Page 1

    ... Consumer IR modes. All of the SCE modes use Synchronous DMA. The IrCC offers flexible signal routing and programmable output control through the Raw mode interface, General Purpose Data pins and Output Multiplexer. Chip-level address decoding is required to access the IrCC register sets. I/O and Ultra I/O infrared 1 ...

  • Page 2

    ... REGISTER BLOCK FOUR ............................................................................................................ 38 ACE UART............................................................................................................................................ 40 REGISTER DESCRIPTION........................................................................................................... 40 SCE ...................................................................................................................................................... 55 DESCRIPTION .............................................................................................................................. 55 FRAMING ...................................................................................................................................... 55 ACTIVE FRAME INDICATOR ....................................................................................................... 55 IrDA ENCODER............................................................................................................................. 56 CONSUMER IR ENCODER .......................................................................................................... 61 LOOPBACK MODE ....................................................................................................................... 63 BUS INTERFACE I/O ........................................................................................................................... 65 FIFO MULTIPLEXER..................................................................................................................... 65 128-BYTE SCE FIFO..................................................................................................................... 65 DMA............................................................................................................................................... 67 PROGRAMMED I/O ...................................................................................................................... 71 IOCHRDY TIME-OUT.................................................................................................................... 73 ZERO WAIT STATE SUPPORT.................................................................................................... 75 OUTPUT MULTIPLEXER ..................................................................................................................... 76 CHIP-LEVEL IrCC ADDRESSING SUPPORT...................................................................................... 77 AC TIMING ........................................................................................................................................... 78 2 ...

  • Page 3

    ... Clock Generator I Infrared Communications Controller System FIGURE 1 - SMSC IrCC FUNCTIONAL COMPONENTS nACE Bus Interface ISA Controls Databus Data (0-7) MUX Address (0-2) FIFO, DMA, I/O, Interrupts nSCE FIGURE 2 - IrCC ARCHITECTURAL BLOCK DIAGRAM Encoders Raw IR IR Transducer Consumer M odule IR Output M ux ASK IR COM IrDA IR ...

  • Page 4

    ... The Interface Description lists the signals that are required to place the IrCC in a larger chip- level context. There are four groups of signals in this section: PORT signals, HOST BUS controls, SYSTEM controls, and CHIP-LEVEL CONFIGURATION controls. NAME SIZE (BITS) IRRx IRTx NAME ...

  • Page 5

    ... SIZE (BITS) Fast GP Data Fast The Fast pin always reflects the state of Fast, bit 6 of SCE Line Control Register A. The state of Fast is independent of the IrCC Block Controls or the Output Multiplexer. The Fast pin can be used at the chip level for IR Transceiver configuration. NAME ...

  • Page 6

    ... IrCC DRQ output when the DMA Enable bit is inactive. The DMA Enable bit is located in SCE Configuration Register B, bit 0. IRQEN IRQEN is used by the chip-level interface to tristate the IrCC IRQ output when the OUT2 bit is inactive. The OUT2 bit is located in 16550A MODEM Control Register. Power Down The Power Down pin is used by the chip-level interface to put the SCE into low power mode ...

  • Page 7

    ... IR Mode Register Bits Input IR Option Register Location Bits IR Mode Typically part of a 16550A Serial Port Option Register. These values are also part of the IrCC Block Control bits 3-5, Register Block One, Address Zero. IR Location Typically part of a 16550A Serial Port IR Option Register. These values are the IrCC Output Mux bits, Register Block One, Address One ...

  • Page 8

    RAW IR In Raw mode the state of the IR emitter and detector can be directly accessed through the host interface (Figure 3). The IR emitter tracks the Raw Tx Control bit. For example, depending on the state of the ...

  • Page 9

    ... NRZ data stream. The components of this block can also modulate and SCE Rx Enable FIGURE 4 - IRCC CONSUMER IR (TV REMOTE) BLOCK demodulate serial data at programmable bit rates and carrier frequencies. Variable length encoding and all packet framing is handled by system software. Consequently, ...

  • Page 10

    Carrier Frequency Divider The Carrier Frequency Divider register is used to program the ASK carrier frequency for the transmit modulator and receive detector (Figure 5). The divider is eight bits wide. The input clock to the Carrier Frequency Divider is ...

  • Page 11

    ... The Transmit and Receive Bit Rate Divider register is used to extract a serial NRZ data stream for the IrCC SCE. The divider is eight bits wide. The input clock to the Bit Rate Divider is 100KHz (Carrier Frequency Divider input clock ÷ 16). The relationship between the ...

  • Page 12

    The Programmable Receive Carrier Sense register is used to program the Consumer IR decoder to detect the presence of IR energy in a wide-to-narrow range of carrier frequencies. The register is two bits wide. Table 11 - Receive Carrier Sense ...

  • Page 13

    ... For continuous periods of high or low data without transitions, the IrCC samples the signal level in the center of each incoming bit period. Using the Receiver Bit Cell Synchronization mechanism, any transition resets the timer that is ...

  • Page 14

    ... Two implementations have been provided in this block of the IrCC, IrDA SIR and Sharp ASK IR. IrDA SIR allows serial communication at baud rates up to 115K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the beginning of the serial bit time ...

  • Page 15

    DATA IRRX nIRRX FIGURE 7 - IrDA RECEIVE TIMING PARAMETER t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud ...

  • Page 16

    DATA IRTX nIRTX FIGURE 8 - IrDA TRANSMIT TIMING PARAMETER t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width ...

  • Page 17

    DATA IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX FIGURE 9 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING PARAMETER t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output “On” t4 Modulated Output ...

  • Page 18

    DATA IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX FIGURE 10 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING PARAMETER t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output “On” t4 Modulated Output ...

  • Page 19

    ... SIR-Physical Layer Specification, Version 1.1, October 17, 1995, the SIR-Link Access Protocol (IrLAP), Version 1.0, UART SCE FIGURE 11 - IRCC IRDA BLOCK DIAGRAM SIR Interaction Pulse The SIR Interaction Pulse (SIP) is intended to guarantee non-disruptive coexistence with SIR- only systems which might otherwise interfere with Fast IR links ...

  • Page 20

    ... FIGURE 12 - SIR INTERACTION PULSE The SIR Interaction Pulse is controlled by the IrCC configuration register SIP ENABLE bit and a timer. The IrCC transmits an SIR Interaction Pulse every 500ms when the SIP enable is active, an IrDA FIR mode has been selected, and the transmitter or receiver is not otherwise engaged ...

  • Page 21

    ... The IrCC can account for system-dependent limitations such as long interrupt latencies and transceiver stabilization times by increasing the number of STA flags at the beginning of every HDLC frame (Figure 14). BOF COUNT register Appends 0 - 4095 Flags to Beginning of Frame STA STA '01111110' '01111110' binary binary FIGURE 14 - EXTENDED BEGINNING-OF-FRAME ...

  • Page 22

    ... CRC binary binary FIGURE 15 - BRICK WALLED HDLC FRAMES 4PPM BOF Counting The IrCC can account for system-dependent limitations such as long interrupt latencies and transceiver stabilization times by increasing the number of PA flags at the beginning of every 4PPM frame (Figure 16). The BOF COUNT register contains the number ...

  • Page 23

    Back-to-back, or brick walled frames are allowed with 32 or more PA flag bytes between the STO field of the first frame and the STA field of the second frame. BW COUNT register Inserts 0 - 4095 PA Bytes between ...

  • Page 24

    ... The IrCC is partially enabled through binary controls found in two 8-byte register banks. The banks, the ACE550 UART Controls and the SCE Controls, are selected with the nACE and nSCE register-bank selector inputs found in the Interface Description. If nACE is zero, the three least significant bits of ...

  • Page 25

    ... The IrCC SCE Registers are arranged in 7-byte blocks. Of the eight possible register blocks, five are used in this implementation. Table 13 - SCE Register Addressing BLOCK ADDRESS ...

  • Page 26

    ... The Master Block Control Register contains the IrCC Power Down bit, two reset bits, the Master Interrupt Enable bit, and the Register Block Select lines (Table 14). Table 14 - SCE Master Block Control Register Address Direction R/W power down Register Block Select, bits 0-2 The Register Block Select bits enable access to each of the eight possible register blocks ...

  • Page 27

    Register Block Zero contains the SCE Data Register, the Interrupt Control/Status registers, the Line Control/Status registers, and the Bus Status register (Table 15). Address Directio R active frame 0 ...

  • Page 28

    When this bit is one, an End of Message has occurred. The EOM indicates the end of an IrDA FIR EOF or Abort. During Consumer IR messages EOM also indicates FIFO underruns/ overruns and DMA Terminal Counts. Reading the Interrupt ...

  • Page 29

    ... SCE FIFO. The FIFO Reset bit is automatically set to zero following the re-initialization. Fast, bit 6 The Fast bit controls the state of an uncommitted IrCC output, Fast. The bit is read/write. General Purpose Data, bit 5 The General Purpose Data bit controls the state bit is read/write. ...

  • Page 30

    ... Brick Wall, bit 4 When the Brick Wall bit is active the IrCC sends back-to-back IrDA FIR frames separated by the number of additional flags specified in the brick wall count register. NOTE: BOF counts do not apply during brick walled messages ...

  • Page 31

    BRICK DATA WALL DONE FIFO ENABLE BIT EMPTY Message Count, bits The four ...

  • Page 32

    ... The Time-Out bit is the IOCHRDY time-out error bit. The Time-Out bit when set to one indicates that an IOCHRDY time-out error has occurred. Time-Out is reset by the IrCC System Reset (see Interface Description) following a read of the Bus Status register, and following a Master Reset (see Master Block Control Register). ...

  • Page 33

    ... For example, if the IRRx pin in the Output Multiplexer is one and the Rx Polarity bit is zero, the signal is inactive and therefore decoded as a one. The IrCC Tx Polarity bit (bit 1) is equivalent to the Transmit Polarity bit in the configuration chip-level configuration space of earlier devices; ...

  • Page 34

    ... Inactive outputs depend on the state of the Tx Polarity bit when the Output Mux bits are both high, otherwise inactive outputs are always low. The Output Mux bits are equivalent to the 93X IR Option Register bits 6-7. The IR Table 21 - IrCC Output Multiplexer ...

  • Page 35

    ... FIFO Threshold values mode is enabled (Table 23). DMA Enable, bit 0 DMA Enable is connected to a signal in the Interface Description called DMAEN that is used by the chip-level interface to tristate the IrCC DMA controls when the DMA interface is inactive. When the DMA Enable bit is one, the one, the DMA host interface is active (Table 23) ...

  • Page 36

    Register Block Two contains the Consumer IR Address Direction R/W sync bit R R Consumer ...

  • Page 37

    ... Register Block Three contains the IrCC Block Identifier Registers. These read-only registers Table 25 - Register Block Three Address Direction SMSC ID (Addresses The SMSC ID registers contain a 16-bit manufacturer identification code ...

  • Page 38

    Register Block Four contains the IrDA control registers. These registers control the IrDA Table 26 - SCE Register Block Four Address Direction R/W 1.152 selec R ...

  • Page 39

    SCE transmitter during loopback testing. NOTE: only the Tx Data Size register is used for IrDA FIR loopback ...

  • Page 40

    ... Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers. The Serial Port registers are located at sequentially increasing addresses above these base addresses. The SMSC IrCC UART register set is described below REGISTER NAME ...

  • Page 41

    ... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SMSC IrCC. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers ...

  • Page 42

    Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writting to this bit has no ...

  • Page 43

    FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT 3 BIT 2 BIT 1 BIT INTERRUPT SET ...

  • Page 44

    Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial ...

  • Page 45

    This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit logic "0", the nDTR output is forced to ...

  • Page 46

    FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have ...

  • Page 47

    MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state ...

  • Page 48

    The Reset Function Table (Table 30) details the effect of the Reset input on each of the registers of the Serial Port. FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", ...

  • Page 49

    XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: - Bit 0=1 as long as there is one byte in the RCVR FIFO. - Bits specify which error(s) have occurred. ...

  • Page 50

    REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read LSR INTRPT (RCVR Data Ready) ...

  • Page 51

    REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt Enable Register DLAB = 0 ADDR = 2 Interrupt Ident. ...

  • Page 52

    Table 31 - Register Summary For An Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 2 Data Bit 3 Enable Enable Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) Interrupt ID ...

  • Page 53

    FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU ...

  • Page 54

    IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 19 - SERIAL PORT TIMING ...

  • Page 55

    DESCRIPTION The SCE is a half-duplex synchronous serial communications controller that controls data flow between the Bus Interface I/O block and the IrDA FIR and Consumer IR (TV 8 Transmit Controls 8 Receive FIGURE 20 - SCE BLOCK DIAGRAM FRAMING ...

  • Page 56

    Transmit nActiveFrame goes active as soon as the Consumer IR transmitter starts modulating the SCE data stream. nActiveFrame becomes inactive as soon as the transmit register is empty. Receive nActiveFrame goes active as soon as the Consumer IR receiver detects ...

  • Page 57

    The SCE IrDA-mode transmitter is enabled by setting the appropriate SCE MODES bits in SCE Line Control Register B. If the FIFO Threshold is zero, message transmission begins as soon as transmit mode has been enabled and there is data ...

  • Page 58

    BOF Active Frame EOM EOM Interrupt Tx Enable Data Done FIFO Empty FIGURE 24 - IrDA FIR TX MESSAGE TIMING (SOFTWARE CRC) When active, the DATA DONE flag in Register Block Zero, Line Control Register A alerts the transmitter that ...

  • Page 59

    ... FIFO Full EOM Interrupt Active Frame Int. Rx Enable FIGURE 27 - IrDA FIR RX ABORT ON OVERRUN TIMING indicators in the IrCC registers. When a valid BOF is detected, the EOM from the previous message is disabled, errors are reset, and an The nActive Frame Interrupt is sent (Figure 26). EOM and the EOM Interrupt are enabled following an active FCS ...

  • Page 60

    During transmit if the CRC Select control is low the FCS is assumed to be part of the message payload data sent from the Host and the hardware CRC generator is not engaged (Figure FIFO Empty EOM CRC Select Data ...

  • Page 61

    ... The IrDA FIR pulse and signaling violations listed in this section are considered framing errors. When the Frame Error bit in the IrCC Line Status register is one, a framing error has occurred. The IrDA receiver response to framing errors depends upon when the errors occur. Framing ...

  • Page 62

    Active Frame FIFO Empty EOM Interrupt Tx Enable Tx Reg. Empty FIGURE REMOTE TRANSMIT TIMING Receive Timing The SCE TV Remote receiver can be enabled with the configuration register SCE Modes bits, polled using programmed I/O, and ...

  • Page 63

    The SCE TV Remote receiver will abort on a FIFO Overrun condition. When the overrun Zero D etect Activ e Fram e Activ e Fram e Int. FIFO Full E OM Interrupt R x Enable FIGURE REMOTE ...

  • Page 64

    The FIFO must be loaded with the appropriate transmit data while the Block Control bits in SCE Configuration Register A are set to the required transfer mode with the SCE MODES bits set to Transmit/Receive Disabled. Enough room must remain ...

  • Page 65

    ... Transmit in Figure 34, above, can be satisfied by the inverse of the SCE Modes msb; e.g., nD7. The Databus Multiplexer provides exclusive ISA Bus access to either the 16550A UART or the IrCC SCE depending on the state of Block Mode Controls in the configuration registers. Disabled blocks are tristated from the ISA Bus. SCE ...

  • Page 66

    Host/ SCE access timing, and during loopback tests with synchronous SCE- only access timing where the FIFO is simultaneouly used for transmit and receive. FIFO controls include, separate read/ write lines, FIFO Full and FIFO Not Empty flags, ...

  • Page 67

    Data Bytes in FIFO TxServReq FIFO Int. Enable FIFO Interrupt 1st Service Request FIGURE 35 - FIFO INTERRUPT EXAMPLE DMA The DMA channel works in Single-Byte and Burst ...

  • Page 68

    DMA Burst mode is enabled by setting the DMA Burst bit in SCE Configuration Register B. Demand Mode DMA transfers data ...

  • Page 69

    Disable 32-Clk Countdown & Reset 32-Clk Counter DMA Burst DMA Enable Refresh Interval FIGURE I/OX CLOCK DMA REFRESH COUNT TIMING Burst Mode Transmit Uses FIFO Threshold for Triggered Transmit. The IrDA 4PPM transmit encoder can deplete the ...

  • Page 70

    ...

  • Page 71

    Programmed I/O mode is selected when the DMA Enable bit in SCE Configuration Register B is zero trin pty FIGURE ...

  • Page 72

    String Move DMA Enable FIFO FULL IOW FIFO Data WRITE FIGURE 43 - PROGRAMMED I/O WRITE TIMING FIFO Interrupt Interface Transmit Description Transmitting messages with Programmed I/O using FIFO Interrupt requires writing a fixed number of data bytes, usually related ...

  • Page 73

    Receive Description Receiving messages with Programmed I/O using FIFO Interrupt requires reading a fixed number of data bytes, usually related to the threshold, whenever the FIFO Interrupt becomes active. An appropriate FIFO Threshold value allows the host to efficiently satisfy ...

  • Page 74

    String M ove FIFO Not Empty IOCHRDY FIGURE 46 - VALID I/O READ READY CYCLE IOCHRDY Timer The 10us IOCHRDY Timer is initialized when IOCHRDY is active. The timer count sequence is activated when IOCHRDY goes inactive. IOCHRDY becomes active ...

  • Page 75

    ... IrCC to indicate that an access cycle shorter than the standard I/O cycle can be executed. NOTE: the names nSRDY & nNOWS can be used interchangeably. nSRDY is enabled by the No Wait bit in SCE No Wait nSRDY The Interaction of nSRDY and IOCHRDY nSRDY and IOCHRDY determine the three types ...

  • Page 76

    ... Consumer IR TV remote controls. There are GP Data pins that always reflects the state of General Purpose Data & Fast bits (5-6) of Line Control Register A, in Register Block Zero, Address Four. The state of the G.P. Data pins is independent of the IrCC Block Controls or the Output Multiplexer. Block Tx Output Rx Aux ...

  • Page 77

    ... Table 33 - IrCC Address Decode at '400'hex HEX ADDRESS 2F8 - 2FF 6F8 - 6FF All other registers in the IrCC register banks (Figure 50). Table 33 illustrates a chip-level IrCC address decoder using a base address of 2F8 for the ACE UART and 2F8+400 or 6F8 for the SCE registers. ACE ...

  • Page 78

    IR RX PULSE REJECTION ENCODER 4PPM HDLC 1.152Mbps HDLC .576Mbps IrDA SIR Consumer IR IRDA 4PPM Bit Rate Tolerance TBD of Bit Rate Rx Pulse Width Single Pulse Double Pulse IRDA HDLC Bit Rate Tolerance TBD of Bit Rate Max ...

  • Page 79

    ... CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IrCC Rev. 5/10/96 ...