IRCC SMSC Corporation, IRCC Datasheet - Page 24

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IRCC

Manufacturer Part Number
IRCC
Description
INFRARED COMMUNICATIONS CONTROLLER
Manufacturer
SMSC Corporation
Datasheet
The IrCC is partially enabled through binary
controls found in two 8-byte register banks. The
banks, the ACE550 UART Controls and the SCE
Controls, are selected with the nACE and nSCE
register-bank selector inputs found in the
Interface Description.
If nACE is zero, the three least significant bits of
the Host Address Bus decode the 16550A UART
DLAB
X
X
X
X
X
X
X
0
0
0
1
1
A2
0
0
0
0
0
0
1
1
1
1
0
0
A1
Table 12 - 16550A UART Addressing
0
0
0
1
1
1
0
0
1
1
0
0
A0
0
0
1
0
0
1
0
1
0
1
0
1
DIRECTION
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Write
Read
Write
24
control registers.
control bank is addressed.
registers are 8 bits wide.
ACE UART CONTROLS
The table below (Table 12) lists the ACE UART
Control Registers (see the ACE UART section).
Interrupt Identification
REGISTER NAME
Interrupt Enable
Transmit Buffer
Modem Control
Receive Buffer
Modem Status
Divisor (MSB)
Divisor (LSB)
FIFO Control
Line Control
Scratchpad
Line Status
If nSCE is zero, the SCE
All of the IrCC

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