IRCC SMSC Corporation, IRCC Datasheet - Page 26

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

The Master Block Control Register contains the
IrCC Power Down bit, two reset bits, the Master
Interrupt Enable bit, and the Register Block
Select lines (Table 14).
Register Block Select, bits 0-2
The Register Block Select bits enable access to
each of the eight possible register blocks. To
access a register block other than the default (0),
write a 3-bit register block number to the least
significant bits of the Master Block Control
Register.
addresses 0 through 6 will access the registers in
the new block.
rewrite zeros to the register block select bits.
Error Reset, bit 4
Writing a one to the Error Reset bit will return all
of the SCE Line Status Register bits (Register
Block Zero) to their inactive states and reset the
Message Count bits to zero.
Master Interrupt Enable, bit 5
Setting the Master Interrupt Enable to a one
enables all of the SCE interrupts only if their
individual controls are enabled. Setting this bit to
A2
1
Address
A1
1
All subsequent reads and writes to
A0
1
Direction
To return to register block 0,
R/W
Table 14 - SCE Master Block Control Register
power
down
D7
master
reset
D6
Master Block Control Register
master
int en.
D5
26
Address seven is solely reserved for the Master
Block Control register. If the nSCE input is zero,
the MBC is always visible, regardless of the state
of the Register Block Select lines.
a zero disables all SCE interrupts regardless of
the state of their individual enables.
Master Reset, bit 6
Setting the Master Reset bit to a one forces data
in the SCE registers and SCE logical blocks into
the Power-On-Reset state. The Master Reset bit
is reset to zero following the reset operation.
NOTE: The Legacy bits (Register Block One,
Address Zero, Bits D0-D6) are unaffected by
Master Reset.
Power Down, bit 7
Setting this bit to a one causes only the SCE to
enter the low-power state. Power down mode
does not preclude access to the Master Block
Control register so that this mode can be
maintained entirely under software control.
Description
reset
error
D4
D3
D2
register block
select
D1
D0
Default
'00'hex