IRCC SMSC Corporation, IRCC Datasheet - Page 27

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

Register Block Zero contains the SCE Data
Register, the Interrupt Control/Status registers,
the Line Control/Status registers, and the Bus
Status register (Table 15).
Data Register (Address 0)
The Data Register is the FIFO access port.
Typically, the user will only write to the FIFO
when transmitting and read from the FIFO when
receiving. The Host always has read access to
the FIFO regardless of the state of the SCE
Modes bits or the Loopback bit.
access to the FIFO is blocked when the FIFO is
empty. The Host has write access to the FIFO
only when the Loopback bit is inactive and the
SCE Modes bits are zero or Transmit mode is
A2
0
0
0
0
0
1
1
1
Address
A1
0
0
1
1
1
0
0
1
A0
0
1
0
1
1
0
1
0
Directio
R/W
R/W
R/W
R/W
WO
RO
RO
RO
under-
empty
active
frame
active
frame
reset
run
D7
fifo
sce modes
not
bits
Table 15 - Register Block Zero
eom
eom
over
Host read
fast
run
fifo
D6
full
-
Line Status Address Register (write)
enable
mode
mode
frame
time-
error
Interrupt Identification Register
g. p.
data
raw
raw
out
D5
sip
Line Status Register (read)
Interrupt Enable Register
Line Control Register A
Line Control Register B
27
Bus Status Register
Data Register
Description
used during IrDA FIR and Consumer IR
message transactions.
enabled.
blocked when the FIFO is full.
Interrupt Identification Register (Address 1)
Active Frame, bit 7
When this bit is one, an Active Frame has
occurred (see the Active Frame Indicator
section).
that the SCE receiver has detected a valid
incoming IrDA FIR or TV Remote start-of-frame
sequence.
register resets the Active Frame bit.
error
brick
size
wall
raw
D4
fifo
fifo
tx
error
raw
D3
crc
rx
The Active Frame typically indicates
Host write access to the FIFO is
Reading the Interrupt Identification
frame
abort
abort
D2
message
status register
count
address
done
data
D1
D0
Default
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex