IRCC SMSC Corporation, IRCC Datasheet - Page 31

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

Message Count, bits 0 - 3
The four Message Count bits control hardware
access to the Line Status Registers and are
unaffected by the Status Register Address bits.
The Message Count bits also indicate the system
message-state.
Count bits are zero, i.e. the power-up default,
Line Status Register zero is active, although
undefined because no messages have been sent
or received.
incremented after every active frame. At point A
ENABLE
BRICK
WALL
1
1
1
1
0
0
0
0
Message Count (0000)
DONE
DATA
BIT
The Message Count bits are
1
1
0
0
1
1
0
0
For example, if the Message
nActive Frame
EMPTY
FIFO
0
1
0
1
0
1
0
1
FIGURE 18 - MESSAGE COUNT EXAMPLE
AFTER
STATE
EOF
BOF
BOF
BOF
Idle
Idle
Idle
Idle
Idle
Brick Wall Next Message
Multi-Frame Window Complete, Reset Data Done bit
Brick Wall Next Message
Brick Wall Next Message (possible underrun)
Re-enable Transmitter for Next Message
Single Message Complete, Reset Data Done bit
Single Message Complete, Datasize Counter = 0
Single Message Complete, Datasize Counter = 0
31
in Figure 18, for example, the rising edge of
nActive Frame increments Message Count by
one indicating that the first message has been
received; i.e., Line Status Register #1 (status
register address 0) is valid, and Line Status
Register
undefined.
Count
('1000'Binary). NOTE: IrDA messages beyond
eight frames are ignored.
0001
A
register
#2
Hardware prevents the Message
DESCRIPTION
0010
is
currently
from
0011
exceeding
active,
although
eight