IRCC SMSC Corporation, IRCC Datasheet - Page 32

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IRCC

Manufacturer Part Number
IRCC
Description
INFRARED COMMUNICATIONS CONTROLLER
Manufacturer
SMSC Corporation
Datasheet
FIFO Indicators (read-only)
The FIFO Indicators reflect the current status of
the SCE FIFO.
FIFO Not Empty, bit 7
The FIFO Not Empty bit when set to one
indicates that there is data in the SCE FIFO.
FIFO Full, bit 6
The FIFO Full bit when set to one indicates that
there is no room for data in the SCE FIFO.
SCE Configuration Register A (Address 0)
Auxiliary IR, bit 7
When the Auxiliary IR bit is one and the active
device is routed through the Output Multiplexer to
the IR Port or the COM Port, the transmit signal
also appears at the Auxiliary Port.
Block Control, bits 3 - 6
The Block Control bits select one of the eight
IrCC operational modes (Table 19). The three
A2
0
0
0
0
1
1
1
Address
A1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
Direction
R/W
R/W
R/W
aux
D7
output mux
ir
bits
Table 18 - Register Block One
D6
loop-
back
block control
D5
SCE Configuration Register A
SCE Configuration Register B
FIFO Threshold Register
32
bits
lpbck
tx crc
The Time-Out bit is the IOCHRDY time-out error
bit. The Time-Out bit when set to one indicates
that an IOCHRDY time-out error has occurred.
Time-Out is reset by the IrCC System Reset (see
Interface Description) following a read of the Bus
Status register, and following a Master Reset
(see Master Block Control Register).
REGISTER BLOCK ONE
Register Block One contains the SCE control
registers (Table 18). Typically, the controls in
Register Block One are needed to configure the
SCE before message transactions can occur.
low-order Block Control bits are equivalent to the
IR Mode bits in the chip-level configuration space
of earlier devices; e.g., the FDC37C93X IR
Option Register, Serial Port 2, Logical Device 5,
Register 0xF1. Provisions have been made in
legacy devices to accommodate IR Mode
selection
configuration registers or the IrCC Block Control
bits; i.e., the last write from either source
determines the current mode selection and is
visible in both registers.
D4
Description
wait
D3
no
through
duplx
string
move
half
D2
tx po-
burst
larity
dma
either
D1
enable
rx po-
larity
dma
D0
the
Default
chip-level
'02'hex
'00'hex
'00'hex

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