IRCC SMSC Corporation, IRCC Datasheet - Page 65

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

The Bus Interface I/O block contains a 128-byte
FIFO, DMA/Interrupt logic, and multiplexers to
control access to the FIFO and the ISA Bus
(Figure 34).
FIFO MULTIPLEXER
SCE FIFO Access
The FIFO Multiplexer controls the configuration
of the SCE FIFO in the Bus Interface I/O Block.
This configuration can be inferred from the state
of the SCE Modes bits in Line Control Register
B:
disabled, or the transmit mode is enabled, the
FIFO is configured for transmit; otherwise, the
FIFO is configured for receive.
Transmit in Figure 34, above, can be satisfied by
the inverse of the SCE Modes msb; e.g., nD7.
when
the
transmit/receive
16550A UART
Databus Multiplexer
Loopback
Transmit
FIGURE 34 - BUS INTERFACE I/O BLOCK
I/O & Interrupt
ISA Bus
Multiplexer
Control
SCE
FIFO
modes
The signal
are
Loopback
65
128-byte
FIFO
0
0
1
The Databus Multiplexer provides exclusive ISA
Bus access to either the 16550A UART or the
IrCC SCE depending on the state of Block Mode
Controls in the configuration registers. Disabled
blocks are tristated from the ISA Bus.
HOST FIFO Access
The Host always has read access to the FIFO,
regardless of the state of the SCE Modes bits, or
the Loopback bit. The Host has write access to
the FIFO when the Loopback bit is inactive and
the transmit/receive modes are disabled or the
Transmit mode is enabled.
128-BYTE SCE FIFO
FIFO Timing & Controls
The FIFO uses interleaved access timing to allow
simultaneous
Transmit
X
0
1
Function
FIFO In to SCE Rx
FIFO Out to Host Bus
FIFO In to Host Bus
FIFO Out to SCE Tx
FIFO In to SCE Rx
FIFO Out to SCE Tx
FIFO
data
reads
and
data