IRCC SMSC Corporation, IRCC Datasheet - Page 67

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

second service request was not enough data to
DMA
The DMA channel works in Single-Byte and
Burst (Demand) Mode. AEN is high during DMA
transfers. The DMA controls are located in SCE
Configuration Register B.
Enable bit (D0) is one, DMA is enabled. The
DMA Burst Mode bit (D1) controls the DMA
mode. DRQ is further gated by the SCE Modes
bits; e.g., DRQ can only be enabled if either
Transmit or Receive mode has been enabled.
During transmit DRQ remains active as long as
Data Bytes in FIFO 51 50 49 54
FIFO Int. Enable
FIFO Interrupt
TxServReq
FIGURE 36 - DMA SINGLE-BYTE MODE TIMING
DMA Enable
FIGURE 35 - FIFO INTERRUPT EXAMPLE
DM A Burst
When the DMA
1st Service
Request
nDACK
DRQ
AEN
I/Ox
TC
Service Req.
Satisfied
...
67
2nd Service
51 50 49 48 47 46 45 44 49 48
Request
interrupt latency.
the FIFO is not full until TC. During receive DRQ
remains active as long as the FIFO is not empty
until TC.
Single-Byte Mode
Single-Byte mode is enabled by resetting the
DMA Burst bit in SCE Configuration Register B.
Single-Byte DMA transfers one data byte for
each DRQ (Figure 36). Terminal Count occurs
only once, during the last byte of data block.
Serv. Req. Satisfied
(long int. latency)
3rd Service
Request
...