IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 26

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

REGISTER BLOCK ZERO
Register Block Zero contains the SCE Data
Register, the Interrupt Control/Status registers,
the Line Control/Status registers, and the Bus
Status register (Table 15). Typically, the controls
Data Register (Address 0)
The Data Register is the FIFO access port.
Typically, the user will only write to the FIFO
when transmitting and read from the FIFO when
receiving. The host always has read access to
the FIFO regardless of the state of the SCE
Modes bits or the Loopback bit.
access to the FIFO is blocked when the FIFO is
empty. The host has write access to the FIFO
only when the Loopback bit is inactive and the
SCE Modes bits are zero or Transmit mode is
enabled.
blocked when the FIFO is full.
Interrupt Identification Register (Address 1)
A2
0
0
0
0
0
1
1
1
ADDRESS
A1
0
0
1
1
1
0
0
1
A0
Host write access to the FIFO is
0
1
0
1
1
0
1
0
DIRECTION
R/W
R/W
R/W
R/W
WO
RO
RO
RO
under-
empty
active
frame
active
frame
reset
run
not
D7
fifo
sce modes
bits
Table 15 - Register Block Zero
Host read
over-
eom
eom
fast
run
D6
fifo
full
Line Status Address Register (write)
reserved
enable
mode
mode
frame
Interrupt Identification Register
time-
error
g. p.
data
raw
raw
D5
sip
out
Line Status Register (read)
Interrupt Enable Register
Line Control Register A
Line Control Register B
26
Bus Status Register
DESCRIPTION
Data Register
in Register Block Zero are used during IrDA FIR
and Consumer IR message transactions.
and registers marked “reserved” in the table
below cannot be written and return 0s when read.
Programmers must set reserved bits to 0 when
writing to registers that contain reserved bits.
When an interrupt is active the associated
interrupt identifier bit in the IID register is also
active regardless of the state of its individual
interrupt enable or the Master Interrupt Enable,
except for the FIFO Interrupt.
Interrupt Enable and the individual Interrupt
Enables serve only to enable the IID register
interrupts onto the Interrupt Request bus IRQ
shown in the Interface Description.
error
brick
size
raw
wall
D4
fifo
fifo
tx
memory count
busy
busy
error
raw
crc
D3
IR
IR
rx
frame
abort
abort
D2
message
count
status register
reserved
reserved
address
done
data
D1
reserved
frame
rsrvd
valid
D0
The Master
DEFAULT
‘00’hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
Bits