IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 27

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IRCC2.0

Manufacturer Part Number
IRCC2.0
Description
Infrared Communications Controller
Manufacturer
SMSC Corporation
Datasheet
Active Frame Interrupt, bit 7
When this bit is one, an Active Frame has
occurred (see the Active Frame Indicator section
on page 59). The Active Frame interrupt typically
indicates that the SCE receiver has detected a
valid incoming IrDA FIR or Remote Control start-
of-frame sequence.
Identification register resets the Active Frame
Interrupt bit.
EOM Interrupt, bit 6
When this bit is one, an End of Message has
occurred. The EOM Interrupt indicates the end
of an IrDA FIR EOF or Abort. During Consumer
IR messages EOM Interrupt
underruns/overruns and DMA Terminal Counts.
Reading the Interrupt Identification register
resets the EOM Interrupt bit.
Raw Mode Interrupt, bit 5
When this bit is one, a Raw Mode interrupt has
occurred. The Raw Mode Interrupt indicates that
the Raw Rx Control bit has gone active. Reading
the Interrupt Identification register resets the Raw
Mode Interrupt bit.
FIFO Interrupt, bit 4
When this bit is one, a FIFO Interrupt has
occurred. The FIFO Interrupt indicates that the
FIFO Interrupt Enable is active and either a
TxServReq or a RxServReq has occurred. The
FIFO Interrupt bit is cleared when the interrupt is
disabled; i.e., reading the Interrupt Identification
register does not reset the FIFO Interrupt bit (see
the FIFO Interrupt section on page 72).
IR Busy, bit 3
The IR Media Busy hardware sets the IR Busy bit
in the IID high if an infrared pulse that is greater
than T
except during message transmit or during the IR
Half Duplex Timeout following message transmit.
The
independently of the IR Rx Pulse Rejection
filters, the programmed receive data rate, or the
state of the ACE or SCE Rx Enables (see Figure
51). Reading the IID register will reset the IR
Busy bit. The IR Busy bit is also reset following
T
PW_MIN
PW_MIN
IR
can be defined as 20ns#T
Media
has occurred at the receiver input,
Busy
Reading the Interrupt
hardware
indicates FIFO
PW_MIN
operates
#30ns
27
Master Reset and POR. If the IR Busy Enable
bit is high, the IR Busy Interrupt is enabled onto
the Interrupt Request bus IRQ if the master
Interrupt Enable is also active.
Enable bit does not affect the IR Busy bit in the
IID. PROGRAMMER’S NOTE: The IR Busy bit
may be unintentionally activated during IR Mode
changes.
Interrupt Enable Register (Address 2)
Setting any of the bits in this register to one
enables the associated interrupt (see the
Interrupt Identification Register). Interrupts will
only occur if both the interrupt enable bit and the
Master Interrupt Enable bit (see the Master Block
Control Register) are active.
The interrupt enables do not affect the state of
the interrupts, except for the FIFO Interrupt. For
example, a Raw Mode interrupt that occurs while
the Raw Mode Interrupt Enable is inactive will be
visible in the IID register but will not affect IRQ.
Line Status Register(s) (Address 3)
Error Indicators (read-only)
There are eight Line Status Registers at address
3. Each register is read-only and is accessed
using the three Status Register Address bits,
also located at this address.
Underrun, FIFO Overrun, Frame Error, Size
Error, Frame Abort, and CRC Error flags indicate
the status of any one of eight IrDA FIR message
frames. The Error Indicators, in all registers, are
reset following a Master Reset, Power-On-Reset,
and Error Reset (see the Master Block Control
Register).
status register only (see the Message Count bits)
are reset following a valid IrDA BOF sequence.
FIFO Underrun, bit 7
The FIFO Underrun bit gets set to one when the
IrDA FIR transmitter runs out of FIFO data and
the Data Done bit is not active.
FIFO Overrun, bit 6
The FIFO Overrun bit gets set to one when the
IrDA FIR receiver tries to write data to the FIFO
when the FIFO Full flag is active.
The error indicators for the current
The IR Busy
The FIFO

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