IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 30

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

transferred and the DMA terminal count or the
FIFO Empty flags have not been activated the
next message is brick walled to the previous
Message Count, bits 0 - 3
The four Message Count bits control (internal)
hardware access to the Line Status Registers
and are unaffected by the Status Register
Address bits (see the Multi-Frame Window
Support section on page 67).
Count bits also indicate the system message-
state. For example, if the Message Count bits
are zero, i.e. the power-up default, Line Status
Register zero is active, although undefined
because no messages have been sent or
received.
Message Count (0000)
ENABLE
BRICK
WALL
1
1
1
1
0
0
0
0
nActive Frame
The
DONE
DATA
BIT
1
1
0
0
1
1
0
0
Message
EMPTY
FIFO
FIGURE 18 - MESSAGE COUNT EXAMPLE
0
1
0
1
0
1
0
1
Count bits
Table 17 - Message Flow Control
The Message
AFTER
STATE
EOF
BOF
BOF
BOF
Idle
Idle
Idle
Idle
Idle
0001
are
A
Brick Wall Next Message
Multi-Frame Window Complete, Reset Data Done bit
Brick Wall Next Message
Brick Wall Next Message (possible underrun)
Re-enable Transmitter for Next Message
Single Message Complete, Reset Data Done bit
Single Message Complete, Datasize Counter = 0
Single Message Complete, Datasize Counter = 0
30
message (Table 17).
software controlled only. Note: BOF counts do
not apply during brick walled messages.
incremented after every active frame. At point A
in Figure 18, for example, the rising edge of
nActive Frame increments Message Count by
one indicating that the first message has been
received. This means that Line Status Register
#1 (status register address 0) is valid, and Line
Status Register #2 is currently active, although
undefined.
Count
('1000'Binary).
eight frames are ignored.
0010
register
DESCRIPTION
Hardware prevents the Message
Note: IrDA messages beyond
0011
from
The Brick Wall bit is
exceeding
eight