IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 32

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

REGISTER BLOCK ONE
Register Block One contains the SCE control
registers (Table 18). Typically, the controls in
Register Block One are needed to configure the
SCE before message transactions can occur.
SCE Configuration Register A (Address 0)
Auxiliary IR, bit 7
When the Auxiliary IR bit is one and the active
device is routed through the Output Multiplexer to
the IR Port or the COM Port, the transmit signal
also appears at the Auxiliary Port.
Block Control, bits 3 - 6
The Block Control bits select one of the eight
IrCC 2.0 operational modes (Table 19).
A2
0
0
0
0
1
1
1
Address
A1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
Directio
R/W
R/W
R/W
R/W
R/W
R/W
RO
n
MFW
MBC
FC7
aux
D7
output mux
ir
7
bits
Table 18 - Register Block One
tx pw
MBC
FC6
limit
D6
6
reserved
rx pw
reject
The
loop-
MBC
back
block control
FC5
D5
Message Byte-Count (high byte)
Message Byte-Count (low byte)
5
SCE Configuration Register A
SCE Configuration Register B
SCE Configuration Register C
FIFO Threshold Register
bits
32
lpbck
tx crc
MBC
FC4
D4
Bits and registers marked “reserved” in the table
below cannot be written and return 0s when read.
Programmers must set reserved bits to 0 (zero)
when writing to registers that contain reserved
bits.
FIFO COUNT
three low-order Block Control bits are equivalent
to the IR Mode bits in the chip-level configuration
space of earlier devices; e.g., the FDC37C93x IR
Option Register, Serial Port 2, Logical Device 5,
Register 0xF1. Provisions have been made in
legacy devices to accommodate IR Mode
selection
configuration registers or the IrCC 2.0 Block
Control bits; i.e., the last write from either source
determines the current mode selection and is
visible in both registers.
4
Description
reserved
MBC
MBC
FC3
wait
D3
no
11
3
through
duplx
string
move
MBC
MBC
FC3
half
D2
10
2
tx po-
larity
burst
MBC
MBC
dma
FC1
D1
DMA Refresh
either
1
9
Count
enable
rx po-
MBC
MBC
larity
dma
FC0
D0
the
0
8
chip-level
Default
'02'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
'03'hex