IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 34
IRCC2.0
Manufacturer Part Number
IRCC2.0
Description
Infrared Communications Controller
Manufacturer
SMSC Corporation
Datasheet
1.IRCC2.0.pdf
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SCE Configuration Register B (Address 1)
Output Mux, bits 7 - 6
The
Multiplexer port for the active encoder/decoder
(Table 21). When D[7:6]=1,1 in Table 21 inactive
outputs depend on the state of the Tx Polarity bit,
otherwise inactive outputs are zero. The Output
Mux bits are equivalent to the FDC37C93x IR
Option Register bits 6-7. The IR Location Mux,
bit 6, in the FDC37C93x IR Option Register is
Loopback, bit 5
The Loopback bit configures the FIFO and
enables the transmitter/receiver for loopback
testing (see the Loopback Mode section on page
68). The SCE MODES bits must be set to zero
before activating the Loopback bit.
Loopback bit is one, the SCE enters a full-duplex
mode with internal loopback capability for testing.
The
reconfigured for either transmit or receive. The
128-byte FIFO input is connected to the SCE
receiver output, the FIFO output is connected to
the SCE transmit input. For IrDA FIR loopback
tests
LOOPBACK
Output
CRC
BIT
0
0
1
1
1
1
generator
Mux
SELECT
CRC
bits
0
1
0
0
1
1
D7
0
0
1
1
can
select
Table 22 - Hardware CRC Programming
Table 21 - IrCC 2.0 Output Multiplexer
LOOPBACK TX
be
D6
0
1
0
1
CRC BIT
the
selectively
When the
X
X
0
1
0
1
Output
Active Device to COM Port (default)
Active Device to IR Port
Active Device to AUX Port
Outputs Inactive
the
34
MUX. MODE
equivalent to Output Mux bit, D6;
(Reserved)
Register is equivalent to Output Mux bit, D7.
Provisions have been made in legacy devices to
accommodate Output Multiplexer port selection
through
registers or the Output Mux bits; i.e., the last
write from either source determines the current
port selection and is visible in both registers.
Loopback bit must be set to zero to exit loopback
mode. Consumer IR loopback tests reset the
Loopback bit automatically when the Rx Data
Size register reaches zero. Provisions must be
made following loopback tests in all modes to
verify the Rx message data in the FIFO.
Loopback Transmit CRC, bit 4
When the Loopback Transmit CRC bit is set to
one, the CRC generator is used by the
transmitter during loopback testing regardless of
the state of the CRC Select bit. Otherwise, the
CRC generator is connected to the receiver
(Table 22).
No CRC Generation, No CRC Checking
No CRC Generation, No CRC Checking
CRC Generation, No CRC Checking
CRC Checking, No CRC Generation
CRC Generation, No CRC Checking
CRC Generation, CRC Checking
either
in
DESCRIPTION
the
the
FDC37C93x IR
chip-level
HARDWARE
configuration
Option
bit 7
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