IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 36

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

programmed in the Rx Data Size register in SCE
Register Block Four; where
For example, if the Rx Data Size register is
programmed for 2048 (0x0800) bytes (the
maximum sized IrDA message) and the Message
Byte Count Register is 0x0000 following the
message reception, the actual size of the
received message is 2048 bytes. The message
byte counts are reset to 0x0000 at POR, Master
Reset, and Error Reset (see the SCE Master
Block Control register).
Message Byte Count Low Byte (Address 4)
This register contains the lower byte of the
Message Byte Counts.
Tx PW Limit, bit 6
The Tx PW Limit bit enables hardware designed
to restrict the IR transmit pulse width (see the
Transmit Pulse Width Limit section on page 83).
If Tx PW Limit = 0, The TRANSMIT PULSE
WIDTH LIMIT hardware is defeated and no
transmit pulse width restrictions are made. If Tx
PW Limit = 1, The TRANSMIT PULSE WIDTH
LIMIT hardware will prevent pulses larger than
100Fs with a 25% duty cycle from appearing at
the IrCC TX output ports.
Actual Byte Count = Rx Data Size - Message
Byte Count
MFW
BIT
0
1
Fixed Frame Mode (default):
Variable Frame Mode:
MFW Frame length determined by Tx Data Size
Register, unlimited messages
MFW Frame length determined by Message Byte
Counts, eight messages max.
Table 24 - MFW Bit Encoding
36
Message Byte Count High Byte (Address 5)
Bits D[3:0] in this register contain the upper
nibble of the Message Byte Counts. The upper
nibble D[7:4] of Address 5 is reserved. Reserved
bits cannot be written and return 0 when read.
SCE Configuration Register C (Address 6)
MFW, bit 7
The MFW bit determines whether Multi-frame
windows use the Tx Data Size Register or the
Message Byte Count Registers to determine the
frame size per message during transmits. Table
24 summarizes the encoding of the MFW bit.
See the Multi-Frame Window Support section on
page 67 for more details.
Rx PW REJECT, bit 5
The Rx PW Reject bit is used to defeat the IR Rx
pulse width rejection filter for the 4PPM IrDA
decoder. If Rx PW Reject = 1 (active) the existing
4PPM Rx pulse width rejection filtering is
enabled. If Rx PW Reject = 0 (inactive) the
4PPM Rx pulse width rejection filter is disabled,
although the receiver will not see pulses that are
less than TPW_MIN (see IR Busy, bit 3, on page
27). Figure 51 contains a T
that might be used to fulfill the IR rx pulse width
rejection filtering requirement.
DESCRIPTION
PW_MIN
detector/filter