IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 40

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

REGISTER BLOCK FOUR
Register Block Four contains the IrDA control
registers.
message framing parameters, HDLC clock
speed, and hardware CRC selection.
IrDA Control Register/BOF Count High
(Address 0)
1.152 Select, bit 7
When the 1.152 Select bit is one, the IrDA 1.152
Mbps HDLC-type FIR data rate is selected.
Otherwise the 0.576 Mbps rate is chosen. This
bit only applies to the SCE clock when the Block
Control bits select Mode 2, IrDA HDLC.
CRC Select, bit 6
When the CRC Select bit is one, a hardware-
generated CRC is appended to the frame
payload
transactions (Table 22).
BOF Count High, bits 0 - 3
The BOF Count specifies the number of
additional flags that are used in a BOF
sequence. For example, at 1.152 Mbps, insert
the BOF Count number of additional flag
characters ('7E'hex) at the start of every frame,
excluding brick walled frames. At 4 Mbps insert
the BOF Count number of additional PA bytes at
the start of every frame, excluding brick walled
frames. The BOF Count is a 12 bit value. This
register, BOF Count High, is the BOF Count
upper nibble.
A2
0
0
0
0
1
1
1
Address
A1
0
0
1
1
0
0
1
data
These registers control the IrDA
A0
0
1
0
1
0
1
0
during
Direction
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IrDA
select
1.152
D7
brick wall count (high nibble)
Table 28 - SCE Register Block Four
FIR
select
message
crc
D6
reserved
The
brick wall count (low byte)
D5
tx data size (low byte)
rx data size (low byte)
IrDA Control Register
reserved
40
bof count (low byte)
Description
registers are read/write. Bits and registers
marked “reserved” in the table below cannot be
written and return 0s when read. Programmers
must set reserved bits to 0 (zero) when writing to
registers that contain reserved bits.
BOF Count Low (Address 1)
The BOF Count Low register is the lower byte of
the BOF Count.
Brick Wall Count Low (Address 2)
The Brick Wall Count register specifies the
number of additional interframe padding flags
used for brick walled messages. The Brick Wall
Count is a 12 bit value. The Brick Wall Count
Low register is the Brick Wall Count lower byte.
BW Count High/Tx Data Size High
(Address 3)
Brick Wall Count High, bits 4 - 7
The BW Count High register is the upper nibble
of the Brick Wall Count.
Tx Data Size High, bits 0 - 3
The Tx Data Size register specifies the IrLAP-
negotiated maximum number of payload data
bytes per IrDA transmit message frame if
software CRC is selected, or the IrLAP-
negotiated maximum number of payload data
bytes minus the number of CRC bytes if
hardware CRC is selected. This register is used
to 1) constrain the transmitter to a valid IrDA
D4
D3
tx data size (high nibble)
rx data size (high nibble)
(high nibble)
D2
bof count
D1
D0
Default
'C0'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex