IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 53

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

status via the LSR. LSR definitions for the FIFO
Polled Mode are as follows:
-
-
DESIRED BAUD
Note
Note
Bit 0=1 as long as there is one byte in the
Bits 1 to 4 specify which error(s) have
RCVR FIFO.
occurred. Character error status is handled
the same way as when in the
mode, the IIR is not affected since EIR bit 2=0.
115200
230400
460800
1
2
RATE
19200
38400
57600
134.5
1200
1800
2000
2400
3600
4800
7200
9600
: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
: The High Speed bit is located in the device configuration space.
110
150
300
600
50
75
GENERATE 16X CLOCK
Table 32 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)
DIVISOR USED TO
32770
32769
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
interrupt
BETWEEN DESIRED AND ACTUAL
PERCENT ERROR DIFFERENCE
53
-
-
-
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still fully
capable of holding characters.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and
Bit 7 indicates whether there are any errors in
shift register is empty.
the RCVR FIFO.
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-
1
SPEED
HIGH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
2
BIT