IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 66

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

Receive Timing
The SCE Remote Control receiver is enabled
with the configuration register SCE Modes bits,
can be polled using programmed I/O, and
Figure 32 illustrates how the Remote Control
receiver operates using DMA. TC disables the
receiver, sends an EOM Interrupt, and resets the
SCE Modes bits to zero.
The SCE Remote Control receiver will abort on a
FIFO Overrun condition.
Active Frame Int.
Tx Reg. Empty
nActive Frame
nActive Frame
EOM Interrupt
FIFO Empty
Active Frame Int.
Rx Enable
Tx Enable
nActive Frame
EOM Interrupt
FIGURE 31 - REMOTE CONTROL MANUAL RX TIMING
FIGURE 30 - REMOTE CONTROL TRANSMIT TIMING
Rx Enable
FIGURE 32 - REMOTE CONTROL DMA RX TIMING
When the overrun
Zero Detect
Note:
TC
Zero Detect
The FIFO
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manually disabled when sufficient data has been
collected (Figure 31). Once enabled, the SCE
receiver will only begin to interpret line data
following the first valid zero detection (see Figure
5 - Remote Control ASK Encode/Decode).
may accumulate extraneous data before the
receiver is fully disabled and may need to be
cleared.
occurs the receiver is disabled, an EOM Interrupt
is sent, and the FIFO is flushed (Figure 33).
Clear FIFO