IRCC2.0 SMSC Corporation, IRCC2.0 Datasheet - Page 67

• Manufacturer Part Number: IRCC2.0
• Description: Infrared Communications Controller
• Manufacturer: SMSC Corporation

MULTI-FRAME WINDOW SUPPORT
The IrCC 2.0 can send and receive up to eight
unacknowledged data frames, i.e. a multi-frame
window.
windows is accomplished with DMA blocks that
are larger than the size of an individual IrDA
message frame.
Configuration Register C (Address 6) on page
32) determines whether multi-frame windows use
the Tx Data Size Register or the Message Byte
Count Registers to determine the frame size per
message in multi-frame windows. All multi-frame
window support can occur in both Brick Walled
and non-Brick Walled modes.
Fixed Frame-Size Windows
Transmit
When MFW bit = 0, the Tx Data Size register is
used to determine the size of message frames in
a multi-frame window.
windows all message frames will be the same
size except for the last frame which may be
smaller.
windows can occur in both Brick Walled and non-
Brick Walled modes.
Fixed frame-size transmit multi-frame
Sending and receiving multi-frame
The MFW bit (see the SCE
FIGURE 33 - REMOTE CONTROL RX ABORT ON OVERRUN
Active Frame Int.
nActive Frame
EOM Interrupt
For fixed frame-size
Rx Enable
FIFO Full
Zero Detect
67
Non-Brickwalled MFWs
To support non-Brick Walled fixed frame-size
multi-frame windows set the SCE Modes bits to
zero and initialize the DMA controller with a
message block that is the size of all of the
messages to be transferred in the window, i.e.,
no larger than Tx Data Size × n, where n is the
number of message frames in the window.
Initialize the Tx Data Size register, choose the
appropriate encoder, start the transmitter, and
wait for an EOM interrupt. Reset and then re-
enable the transmitter DMA block-size ÷ Tx Data
Size times, until all of the messages in the DMA
block have been transferred.
Threshold for the last frame, if necessary.
Brickwalled MFWs
To support Brick Walled multi-frame windows set
the SCE Modes bits to zero and initialize the
DMA controller with a data block that is the size
of all of the messages to be transferred in the
window, i.e., no larger than Tx Data Size × n,
where n is the number of message frames in the
window.
initialize the Brick Wall Count, and set the Brick
Wall bit. Start the transmitter once only and wait
for DMA block-size ÷ Tx Data Size EOF
interrupts until the DMA block has been
transferred.
Receive
Overrun
Choose the appropriate encoder,
Reset the FIFO