SN74LS290D Motorola, SN74LS290D Datasheet - Page 3

• Manufacturer Part Number: SN74LS290D
• Description: DECADE COUNTER 4-BIT BINARY COUNTER
• Manufacturer: Motorola

FUNCTIONAL DESCRIPTION
4-Bit Binary counters respectively. Each device consists of
four master/ slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q 0 output of each device is designed and
specified to drive the rated fan-out plus the CP 1 input of the
device.
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS 1
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP 1 input must be
MR 1
The LS290 and LS293 are 4-bit ripple type Decade, and
A gated AND asynchronous Master Reset (MR 1 MR 2 ) is
Since the output from the divide-by-two section is not
H
H
X
X
X
L
L
RESET/SET INPUTS
MR 2
H
H
X
X
X
L
L
NOTE: Output Q 0 is connected to Input CP 1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
COUNT
COUNT
BCD COUNT SEQUENCE
0
1
2
3
4
5
6
7
8
9
MS 1
LS290 MODE SELECTION
H
L
X
L
X
X
L
MS 2 ) is provided on the LS290 which
Q 0
H
H
H
H
H
L
L
L
L
L
MS 2
LS290
X
H
X
X
L
L
L
Q 1
H
H
H
H
L
L
L
L
L
L
OUTPUT
Q 0
H
L
L
SN54/74LS290
Q 2
H
H
H
H
L
L
L
L
L
L
Q 1
OUTPUTS
L
L
L
Q 3
Count
Count
Count
Count
H
H
L
L
L
L
L
L
L
L
Q 2
L
L
L
FAST AND LS TTL DATA
Q 3
H
L
L
5-468
D
SN54/74LS293
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q 3
C. Divide-By-Two and Divide-By-Five Counter — No external
LS293
A. 4-Bit Ripple Counter — The output Q 0 must be externally
B. 3-Bit Ripple Counter — The input count pulses are applied
externally connected to the Q 0 output. The CP 0 input
receives the incoming count and a BCD count sequence is
produced.
output must be externally connected to the CP 0 input. The
input count is then applied to the CP 1 input and a
divide-by-ten square wave is obtained at output Q 0 .
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP 0 as the
input and Q 0 as the output). The CP 1 input is used to obtain
binary divide-by-five operation at the Q 3 output.
connected to input CP 1 . The input count pulses are applied
to input CP 0 . Simultaneous division of 2, 4, 8, and 16 are
performed at the Q 0 , Q 1 , Q 2 , and Q 3 outputs as shown in
the truth table.
to input CP 1 . Simultaneous frequency divisions of 2, 4, and
8 are available at the Q 1 , Q 2, and Q 3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
RESET INPUTS
MR 1
Note: Output Q 0 connected to input CP 1 .
H
H
L
L
COUNT
COUNT
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
MR 2
LS293 MODE SELECTION
H
H
L
L
TRUTH TABLE
Q 0
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Q 0
L
Q 1
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
OUTPUT
Q 1
OUTPUTS
L
Count
Count
Count
Q 2
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Q 2
L
Q 3
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Q 3
L