LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 172

• Manufacturer Part Number: LM3S308
• Description: Lm3s308 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
9.3.2
9.3.3
172
7.
In One-Shot mode, the timer stops counting after step 7 on page 172. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1.
2.
3.
4.
5.
6.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a.
b.
If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
Write a value of 0x1 for One-Shot mode.
Write a value of 0x2 for Periodic mode.
Preliminary
June 04, 2008