LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 187

• Manufacturer Part Number: LM3S308
• Description: Lm3s308 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x020
Type RO, reset 0x0000.0000
June 04, 2008
Bit/Field
31:11
7:4
10
RO
RO
9
8
3
2
1
0
31
15
0
0
RO
RO
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
30
14
0
0
reserved
RO
RO
TBTOMIS
TATOMIS
29
13
reserved
CBMMIS
reserved
CAMMIS
CBEMIS
RTCMIS
CAEMIS
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
CBEMIS
RO
RO
26
10
0
0
CBMMIS
RO
RO
Reset
25
0x00
0
9
0
0x0
0
0
0
0
0
0
0
TBTOMIS
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCMIS
RO
RO
19
0
3
0
LM3S308 Microcontroller
CAEMIS
RO
RO
18
0
2
0
CAMMIS
RO
RO
17
0
1
0
TATOMIS
RO
RO
16
0
0
0
187